
Section 5 Interrupt Controller
Rev. 1.00 Mar. 02, 2006 Page 94 of 798
REJ09B0255-0100
When the interrupts are requested while IRQ15 to IRQ0 interrupt requests are generated at low
level of
IRQn input, hold the corresponding IRQ input at low level until the interrupt handling
starts. Then put the relevant
IRQ input back to high level within the interrupt handling routine and
clear the IRQnF bit (n
= 15 to 0) in ISR to 0. If the relevant IRQ input is put back to high level
before the interrupt handling starts, the relevant interrupt may not be executed.
The detection of IRQ15 to IRQ0 interrupts does not depend on whether the relevant pin has been
set for input or output. Therefore, when a pin is used as an external interrupt input pin, clear the
DDR bit of the corresponding port to 0 so it is not used as an I/O pin for another function.
A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 5.4.
IRQnE
IRQnF
S
R
Q
IRQn
ISSm
ExIRQn
IRQn interrupt
request
Clear signal
IRQnSCA, IRQnSCB
n = 15 to 7
m = 15 to 7
Note: Switching between the
IRQ6 and ExIRQ6 pins is controlled by the EIVS bit.
Edge/level
detection circuit
Figure 5.4 Block Diagram of Interrupts IRQ15 to IRQ0
(3) KIN15 to KIN0 Interrupts
Interrupts KIN15 to KIN0 are requested by the input signals on pins
KIN15 to KIN0. Functions of
interrupts KIN15 to KIN0 change as follows according to the setting of the EIVS bit in system
control register 3 (SYSCR3).
H8S/2140B Group compatible vector mode (EIVS = 0 in SYSCR3)
Interrupts KIN15 to KIN8 correspond to interrupt IRQ7, and interrupts KIN7 to KIN0
correspond to interrupt IRQ6. The pin conditions for generating an interrupt request,
whether the interrupt request is enabled, interrupt control level setting, and status of the
interrupt request for the above interrupts are in accordance with the settings and status of
the relevant interrupts IRQ7 and IRQ6.
KIN15 to KIN0 interrupt requests can be masked by using KMIMRA and KMIMR.
If the KIN7 to KIN0 pins are specified to be used as key-sensing interrupt input pins, the
interrupt sensing condition for the corresponding interrupt source (IRQ6 or IRQ7) must be
set to low-level sensing or falling-edge sensing.