
Section 16 LPC Interface (LPC)
Rev. 1.00 Mar. 02, 2006 Page 564 of 798
REJ09B0255-0100
Table 16.9 summarizes the methods of setting and clearing these bits, and figure 16.8 shows the
processing flowchart.
Table 16.9
HIRQ Setting and Clearing Conditions
Host Interrupt
Setting Condition
Clearing Condition
HIRQ1
Internal CPU writes to ODR1, then reads 0
from bit IRQ1E1 and writes 1
Internal CPU writes 0 to bit IRQ1E1,
or host reads ODR1
HIRQ12
Internal CPU writes to ODR1, then reads 0
from bit IRQ12E1 and writes 1
Internal CPU writes 0 to bit
IRQ12E1, or host reads ODR1
SMI
(IEDIR2 = 1,
IEDIR3 = 1, or
IEDIR4 = 1)
Internal CPU
writes to ODR2, then reads 0 from bit
SMIE2 and writes 1
writes to ODR3, then reads 0 from bit
SMIE3A and writes 1
writes to TWR15, then reads 0 from bit
SMIE3B and writes 1
writes to ODR4, then reads 0 from bit
SMIE4 and writes 1
Internal CPU
writes 0 to bit SMIE2, or host
reads ODR2
writes 0 to bit SMIE3A, or host
reads ODR3
writes 0 to bit SMIE3B, or host
reads TWR15
writes 0 to bit SMIE4, or host
reads ODR4
SMI
(IEDIR2 = 1,
IEDIR3 = 1, or
IEDIR4 = 1)
Internal CPU
reads 0 from bit SMIE2, then writes 1
reads 0 from bit SMIE3A, then writes 1
reads 0 from bit SMIE3B, then writes 1
reads 0 from bit SMIE4, then writes 1
Internal CPU
writes 0 to bit SMIE2
writes 0 to bit SMIE3A
writes 0 to bit SMIE3B
writes 0 to bit SMIE4
HIRQi
(i = 6, 9, 10, 11)
(IEDIR2 = 1,
IEDIR3 = 1, or
IEDIR4 = 1)
Internal CPU
writes to ODR2, then reads 0 from bit
IRQiE2 and writes 1
writes to ODR3, then reads 0 from bit
IRQiE3 and writes 1
writes to ODR4, then reads 0 from bit
IRQiE4 and writes 1
Internal CPU
writes 0 to bit IRQiE2, or host
reads ODR2
CPU writes 0 to bit IRQiE3, or
host reads ODR3
CPU writes 0 to bit IRQiE4, or
host reads ODR4
HIRQi
(i = 6, 9, 10, 11)
(IEDIR2 = 1,
IEDIR3 = 1, or
IEDIR4 = 1)
Internal CPU
reads 0 from bit IRQiE2, then writes 1
reads 0 from bit IRQiE3, then writes 1
reads 0 from bit IRQiE4, then writes 1
Internal CPU
writes 0 to bit IRQiE2
writes 0 to bit IRQiE3
writes 0 to bit IRQiE4