
Rev. 1.00 Mar. 02, 2006 Page xxxvii of xl
Table 10.5
TPSC2 to TPSC0 (channel 0) ............................................................................... 237
Table 10.6
TPSC2 to TPSC0 (channel 1) ............................................................................... 237
Table 10.7
TPSC2 to TPSC0 (channel 2) ............................................................................... 238
Table 10.8
MD3 to MD0 ........................................................................................................ 240
Table 10.9
TIORH_0 (channel 0) ........................................................................................... 242
Table 10.10
TIORH_0 (channel 0) ....................................................................................... 243
Table 10.11
TIORL_0 (channel 0)........................................................................................ 244
Table 10.12
TIORL_0 (channel 0)........................................................................................ 245
Table 10.13
TIOR_1 (channel 1) .......................................................................................... 246
Table 10.14
TIOR_1 (channel 1) .......................................................................................... 247
Table 10.15
TIOR_2 (channel 2) .......................................................................................... 248
Table 10.16
TIOR_2 (channel 2) .......................................................................................... 249
Table 10.17
Register Combinations in Buffer Operation ..................................................... 267
Table 10.18
PWM Output Registers and Output Pins .......................................................... 272
Table 10.19
Phase Counting Mode Clock Input Pins ........................................................... 275
Table 10.20
Up/Down-Count Conditions in Phase Counting Mode 1.................................. 276
Table 10.21
Up/Down-Count Conditions in Phase Counting Mode 2.................................. 277
Table 10.22
Up/Down-Count Conditions in Phase Counting Mode 3.................................. 278
Table 10.23
Up/Down-Count Conditions in Phase Counting Mode 4.................................. 279
Table 10.24
TPU Interrupts .................................................................................................. 280
Section 11 8-Bit Timer (TMR)
Table 11.1
Pin Configuration.................................................................................................. 300
Table 11.2
Clock Input to TCNT and Count Condition (1) .................................................... 304
Table 11.2
Clock Input to TCNT and Count Condition (2) .................................................... 305
Table 11.3
Registers Accessible by TMR_X/TMR_Y ........................................................... 314
Table 11.4
Input Capture Signal Selection ............................................................................. 323
Table 11.5
Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X ....... 324
Table 11.6
Timer Output Priorities ......................................................................................... 326
Table 11.7
Switching of Internal Clocks and TCNT Operation.............................................. 327
Section 12 Watchdog Timer (WDT)
Table 12.1
Pin Configuration.................................................................................................. 333
Table 12.2
WDT Interrupt Source .......................................................................................... 340
Section 13 Serial Communication Interface (SCI)
Table 13.1
Pin Configuration.................................................................................................. 345
Table 13.2
Relationships between N Setting in BRR and Bit Rate B..................................... 359
Table 13.3
Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 360
Table 13.3
Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 361
Table 13.4
Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 361
Table 13.5
Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 362