
Section 13 Serial Communication Interface (SCI)
Rev. 1.00 Mar. 02, 2006 Page 343 of 798
REJ09B0255-0100
Section 13 Serial Communication Interface (SCI)
This LSI has an independent serial communication interface (SCI) channel. The SCI can handle
both asynchronous and clocked synchronous serial communication. Asynchronous serial data
communication can be carried out with standard asynchronous communication chips such as a
Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication
Interface Adapter (ACIA). A function is also provided for serial communication between
processors (multiprocessor communication function). The SCI also supports the smart card (IC
card) interface based on ISO/IEC 7816-3 (Identification Card) as an enhanced asynchronous
communication function.
13.1
Features
Choice of asynchronous or clocked synchronous serial communication mode
Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously. Double-buffering is used in both the transmitter and the receiver,
enabling continuous transmission and continuous reception of serial data.
On-chip baud rate generator allows any bit rate to be selected
The External clock can be selected as a transfer clock source (except for the smart card
interface).
Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
Four interrupt sources
Four interrupt sources
transmit-end, transmit-data-empty, receive-data-full, and receive
error
that can issue requests.
Asynchronous Mode:
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Receive error detection: Parity, overrun, and framing errors
Break detection: Break can be detected by reading the RxD pin level directly in case of a
framing error
Multiprocessor communication capability