
Section 16 LPC Interface (LPC)
Rev. 1.00 Mar. 02, 2006 Page 507 of 798
REJ09B0255-0100
Section 16 LPC Interface (LPC)
This LSI has an on-chip LPC interface.
The LPC includes four register sets, each of which comprises data and status registers, control
register, the fast Gate A20 logic circuit, and the host interrupt request circuit.
The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz
PCI clock. It uses four signal lines for address/data and one for host interrupt requests. This LPC
module supports I/O read and I/O write cycle transfers. It is also provided with power-down
functions that can control the PCI clock and shut down the LPC interface.
16.1
Features
Supports LPC interface I/O read and I/O write cycles
Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data.
Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME).
Four register sets comprising data and status registers
The basic register set comprises three bytes: an input register (IDR), output register (ODR),
and status register (STR).
I/O addresses from H'0000 to H'FFFF are selected for channels 1 to 4.
A fast Gate A20 function is provided for channel 1.
For channel 3, sixteen bidirectional data register bytes can be manipulated in addition to
the basic register set.
Supports SERIRQ
Host interrupt requests are transferred serially on a single signal line (SERIRQ).
On channel 1, HIRQ1 and HIRQ12 can be generated.
On channels 2, 3 and 4, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated.
Operation can be switched between quiet mode and continuous mode.
The CLKRUN signal can be manipulated to restart the PCI clock (LCLK).
Power-down modes and interrupts
The LPC module can be shut down by inputting the LPCPD signal.
Three pins, PME, LSMI, and LSCI, are provided for general input/output.