Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
100
PM2329 ClassiPI Network Classification Processor Datasheet
Enable Packet Buffer Available Interrupt (PBA)
If this bit is set, an interrupt is generated when a Packet Buffer is available for receiving new packet data
from the external processor.
Enable Result Available Interrupt (RAV)
If this bit is set, an interrupt is generated when there is at least one result in the Result FIFO.
Enable OC Sequence Terminated Interrupt (OCST)
If this bit is set, an interrupt is generated when an entire sequence of OCs has terminated, i.e., processing
for the current packet is over. Upon completion of an OC sequence, the current packet is discarded by
the PM2329.
Interrupt Enable
SINT* is never asserted if this bit is set to
’
0
’
. When
’
1
’
, an interrupt is generated when an interrupting
condition exists and the interrupt enable bit for that condition is set to
’
1
’
as shown below.
4.2.2.11 Status Register (STSR; 8240h)
Access Mode: Read Only, Global
The Status Register provides common information regarding the state of the single or cascaded PM2329
devices. This is a Global Read register, only the Primary PM2329 responds to the read request. The bits
defined hold true for all devices in a cascade of PM2329 devices.
In single channel mode when interrupts are not used, it is possible to process the status using either this
register or the appropriate channel status register.
In multi-chanel mode, this register provides summary status of all the channels. Channel specific
information can be retrieved by reading the channel status registers.
When interrupts are used, this register should be read to clear the OC Sequence Terminated bit.
Bit
Range
63:8
7
6
5
4
3
2
1
0
Size
56
1
1
1
1
1
1
1
1
Name
Value after
Reset
Undefined
0
Undefined
0
1
1
0
0
1
(Reserved)
Result FIFO Full
OC Sequence Halt Condition
OC Sequence Halted
Idle
Packet Buffer Available
Result Available
OC Sequence Terminated
Status Valid