參數(shù)資料
型號: PM2329
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 28/162頁
文件大?。?/td> 1581K
代理商: PM2329
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
Internal Use
Document ID: PMC-2010146, Issue 4
31
PM2329 ClassiPI Network Classification Processor Datasheet
Table 5
Test Signals
Signal Name
JTRST
JTMS
JTDI
JTDO
JTCK
TRISTATE
Ball #
V3
W2
Y1
W3
Y2
AA1
Size
1
1
1
1
1
1
I/O
Description
I
I
I
O
I
I
JTAG Reset (tie LOW during normal operation)
JTAG Mode (tie HIGH during normal operation)
JTAG Data In (tie HIGH during normal operation)
JTAG Data Out (No Connect during normal operation)
JTAG Clock Input (tie LOW during normal operation)
Tristate Mode Select
During normal operation, this signal should be tied
permanently low.
If this signal is asserted high all outputs of the PM2329
are tristated.
Test Control signals
TESTCTL[3:0]
H25
T2
T3
J25
3
I
These test signals are for test and debug purpose only.
During normal device operation, these TESTCTL[3]
should be tied permanently low and TESTCTL[2:0]
should be tied permanently high. For debug purpose, a
provision should be made on the board to drive these
signals low or high.
Test Output signals
TESTOUT[7:0]
AD5
AC7
AC20
AD22
C22
D20
D7
C5
AA2
8
O
These test signals are for test and debug purpose only.
During normal device operation, these signals can be
left unconnected. For debug purpose, these signals
should be routed to test points for observation.
TESTMODE
1
I
Test signal
This test signal is for internal use only.
During normal device operation this signal should be
tied low.
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