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| 型號(hào)： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 43/162頁(yè) |
| 文件大?。?/td> | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
46
PM2329 ClassiPI Network Classification Processor Datasheet
Depending on the write cycle timing, up to 4 additional 64-bit writes can be performed without causing
packet input buffer overflow.
If the DMA source performs a burst write into the PM2329 with data transfers on every clock cycle, it can
perform a number of additional data transfers without causing a data overrun, as shown in Figure 7
.
The
number of additional transfers varies depending on transfer width and mode. In 64-bit SyncBurst mode, it
can perform two additional data transfers after the cycle in which it detects PSPBA deasserted low (since
the internal pipeline is 2 deep). In 64-bit ZBT mode, it can perform data transfers until the cycle in which it
detects PSPBA deasserted low (since the internal and external pipeline is 4 deep). The corresponding
numbers in 32-bit mode are six for SyncBurst mode and four for ZBT mode.
When PSPBA is asserted, the Packet Source acquires the bus and asserts PSCC to indicate to the PM2329
that the present transfer is from the packet source. Assertion of the SWE* in conjunction with SWLE* and/
or SWHE* lines causes the current cycle to be treated as a packet data write cycle and data present on
SD[63:0] is written to the PM2329 on the next SCLK rising edge. A number of such packet data write
cycles could occur in a back-to-back cycle burst. Alternatively, PSCC can be de-asserted while PSPBA is
asserted and the processor can execute read or write cycles interleaved with DMA cycles. PSCC is
generally tied to the DMA Acknowledge signal.
The PM2329 provides an additional signal, PSPD, to allow the DMA Controller to communicate to the
PM2329 the direction of each packet. Packets can be associated with a Direction bit and the PM2329 rules
can be programmed to inspect this Direction bit in header lookups. This signal (if used) must be asserted
during each cycle of packet transfer. If PSPD is not used, packet direction can be signalled via the packet
attribute field.
In order to complete the packet transfer, the PS must assert the PSEOP signal or issue an EOP command
for the last word of the packet to be transferred. This indicates to the PM2329 that the current packet
transfer is complete and the PM2329 can begin processing the packet data. PSEOP would generally be
connected to the Terminal Count signal in a DMA based system.
Systems that do not use this DMA mechanism to perform packet transfers should leave the PSPBA output
signal unconnected and tie the PSEOP, PSPD and PSCC input signals inactive. In such systems, a
processor write to the Packet Buffer Input register can be used to load the packet data into the device. The
Packet Buffer Availaibility status is readable in a PM2329 status register, and End of Packet can be
indicated to the PM2329 by a write to the alternate address of the Packet Buffer Input register.
Table 13
PSPBA Deassertion Delay
PSPBA Deassertion Delay
64-bit Mode
4 clocks
2 clocks
Access Mode
ZBT
SyncBurst
32-bit Mode
4 clocks
6 clocks
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