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參數(shù)資料
| 型號(hào)： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 68/162頁(yè) |
| 文件大?。?/td> | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
71
PM2329 ClassiPI Network Classification Processor Datasheet
4 Registers
4.1 PM2329 Access Modes
The mechanism to access the internal status and programmable locations within the PM2329 device
permits simple and flexible access in a variety of configurations. The access mechanism provides a
consistent interface to the external processor in both single-chip or cascade (multi-chip) configurations.
The PM2329 can be connected to either a 64-bit or a 32-bit interface on the packet processor. The access
mechanism allows multiple contexts on the packet processor to communicate easily with an assigned
channel within the PM2329.
4.1.1 Address Space
The PM2329 address space is divided into Local and Global spaces. The concept of local vs. global
addressing is relevant to the cascade (multi-chip) configuration. Local space in general represents registers
involved with processing functions that are specific to a particular PM2329 device. Global space in general
represents registers involved with processing functions that span all PM2329 devices in the cascade. A
conceptual view of Global and Local register space is considered in Figure 22.
Figure 22 Local vs. Global Register Space; Conceptual View A
Each register within the PM2329 is mapped either to Local or Global address space. The access mode is
determined by the state of the SA[15] address line in any given access cycle. If SA[15] is low, the access is
to the Local space. If SA[15] is high, the access is to the Global space. The other address lines dictate
which specific PM2329 device, and which specific register within the prescribed space of that device, is
accessed.
The PM2329 has three pins (CID[2:0]) which are sampled at reset to assign a unique PM2329 ID Number
(CID #N) to each chip in the cascade. The value on these pins during reset must be set up to assign a serial
number from 0 to N to each PM2329 device, where N varies from 0 to 7. In single chip configuration, the
PM2329 is assigned Cascade ID #0 (or CID #0).
When the Local address space is accessed (SA[15] is low), each PM2329 compares the address lines
SA[14:12] with its CID #N. If they match, then the particular PM2329 device is accessed.
Network
Processor
PM2329
CID #0
aspace
PM2329
CID #1
aspace
PM2329
CID #2
aspace
PM2329
CID #n
aspace
addglobal
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