參數(shù)資料
型號(hào): PM2329
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 158/162頁
文件大?。?/td> 1581K
代理商: PM2329
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
Internal Use
Document ID: PMC-2010146, Issue 4
161
PM2329 ClassiPI Network Classification Processor Datasheet
General Note:
1. The cascade interface timing parameters are specified with reference to SCLK.
2. Number of devices in cascade is limited by the SCLK frequency as follows: 116MHz : 1 device, 100MHz : 2 devices, 77MHz: 3
devices, 66MHz : 4 devices, 50MHz : 8 devices. Note that the number of devices in cascade is also determined by the capacitive
loading due to board layout and the presence of other devices on the system bus.
6.2.6 JTAG Interface Timing
Figure 40 JTAG Interface Timing
Table 42
Cascade Interface Timing Parameters
Item
1
2
3
4
5
6
7
8
9
10
11
12
Parameter
Symbol
Tcocss
Tcocsh
Tcocsv
Tcocds
Tcocdh
Tcocdv
Tcocms
Tcocmh
Tcocmv
Tcems
Tcemh
Tcemv
Conditions
Min.
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
COCS (input mode) setup time
COCS (input mode) hold time
SCLK to COCS (output mode) valid
COCDIN[n] setup time
COCDIN[n] hold time
SCLK to COCDOUT valid
COCM* (input mode) setup time
COCM* (input mode) hold time
SCLK to COCM* (output mode) valid
CEMRQ (input mode) setup time
CEMRQ (input mode) hold time
SCLK to CEMRQ (output mode) valid
1.2
0.5
7.8
3.0
0.5
5.0
1.5
0.5
8.0
1.8
0.5
7.7
ts
J T M S
th
J T M S
J T M S
J T C K
ts
J T D I
th
J T D I
J T D I
tv
JT D O
J T D O
J T C K
J T R S T
tp
J T R S T
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