Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
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Internal Use
Document ID: PMC-2010146, Issue 4
24
PM2329 ClassiPI Network Classification Processor Datasheet
ACLKOUT
R2
1
O
Internal ACLK Output
During normal device operation (TESTMODE is low),
this signal is driven low.
During test mode operation (TESTMODE is high), this
pin outputs a divided by 4 version of the qualified ACLK.
The source of ACLKOUT can either be:
Internal ACLK signal generated by the on-chip PLLA
(when PLLABYPS is low)
- o r-
External ACLKIN input signal (when PLLABYPS is high)
If the ACLK frequency is 232MHz, the corresponding
ACLKOUT will be 50 MHz.
SCLK Output
SCLKOUT
M2
1
O
During normal device operation (TESTMODE is low),
this signal is driven low.
During test mode operation (TESTMODE is high), this
pin outputs the qualified SCLK. The source of
SCLKOUT can either be:
Internal SCLK signal generated by the on-chip PLLS
(when PLLSBYPS is low)
- or -
External SCLK input signal (when PLLSBYPS is high)
System Clock Input
SCLK
N4
1
I
This is the main timing clock input to the PM2329. It
must be active at all times. The maximum clock input
frequency is dictated by the CVDD voltage input level.
Nominal CVDD Max SCLK input
1.5V 100MHz
1.6V 116MHz
PLLSBYPS
N3
1
I
PLLS Bypass
During normal device operation, this signal must be
grounded and its state must not be changed during
operation of the PM2329.
In order to bypass the internal PLLS, this signal must be
forced high and the SCLK clock signal supplied on the
SCLK pin is used to drive the clock internally.
Table 1
Timing and Common Control Signals
Signal Name
Ball # Size
I/O
Description