參數(shù)資料
型號: PM2329
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 108/162頁
文件大?。?/td> 1581K
代理商: PM2329
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
Internal Use
Document ID: PMC-2010146, Issue 4
111
PM2329 ClassiPI Network Classification Processor Datasheet
4.2.2.16 Timer Register (TMR; 8268h)
Access Mode: Read/Write, Global
The contents of this register are used to update the aging information or Timestamp D-Word in the E-
RAM. The Timestamp field of this register is used to update the specific D-Word defined as Timestamp.
The Divider field of this register specifies the frequency at which the Timestamp field should be updated.
This frequency is derived by dividing the system clock (SCLK) by a 15 bit prescaler and then by the
divider field specified in this register. The register can be reprogrammed with a new Divider or Timestamp
by writing to it. Whenever this register is written, the internal prescaler is loaded with the newly written
value.
The Timestamp field is incremented at the following frequency:
( F
SCLK
/(2
15
-Prescaler + 1) ) / Divider
As an example, if the SCLK frequency is 66 MHz, the prescaler output period is 0.4915 msec. As an
example, the table below shows the rate at which the Timestamp will be incremented for some example
settings of Divider value assuming the prescaler was loaded with 0h.
Figure 27 shows an overview of the Timer logic.
Bit
Range
63
62:48
47:44
43:32
31:24
23:0
Size
1
15
4
12
8
24
Name
Value after
Reset
Undefined
0000h
Undefined
000h
Undefined
00 0000h
(Reserved)
Prescaler
(Reserved)
Divider
(Reserved)
Timestamp
Table 25
Timestamp Increment Interval Example (SCLK 66.67 MHz)
Divider
Timestamp
Increment
Interval
2.0133
0.4915
24.576
Unit
0
1
50
sec
ms
ms
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