參數(shù)資料
型號(hào): PM2329
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 42/162頁
文件大小: 1581K
代理商: PM2329
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
Internal Use
Document ID: PMC-2010146, Issue 4
45
PM2329 ClassiPI Network Classification Processor Datasheet
Figure 6 System Interface Register Timing Diagram (ZBT)
2.4.1.3 Packet Source Interface Signals
The PM2329 System interface has four control signals designed to support a dedicated packet processor
configured as a DMA controller. These signals are PSPBA, PSEOP, PSPD and PSCC. This DMA interface
is a write-only interface, and active in single channel mode only.
When the PM2329 has space in the packet buffer to accept packet data, PSPBA signal is asserted. The
signal is deasserted when:
1.
The last available 256-byte segment is being written and either the PSEOP signal is asserted or the
EOP command terminates the current packet transfer, or
2.
The Packet Buffer limit is reached.
The PSPBA signal is deasserted low corresponding to the 27th (64-bit) word written into the last 32-
locations by 64-bits segment (that is, the last 256-byte segment) of the packet input buffer. Due to the
pipelined nature of the device, there will be a certain delay between the external write cycle for the 27th
word and deassertion of PSPBA signal, as noted in Table 13 below.
SCLK
SA[15:3]
SD[63:0]
SCE0*/
SCE1*
SOE*
SRW*
SWHE*
SWLE*
SCE2
WA1
WA2
RA1
RA2
WA3
WA4
Undefined
Undefined
WD1
WD2
RD1
RD2
WD3
WD4
Don
t Care
Don
t Care
Write Cycles
Read Cycles
Write Cycles
Undefined Cycles
Register Read and Write Timing, ZBT Mode
PSCC
PSPD
Don
t Care
Don
t Care
PSEOP
Don
t Care
Don
t Care
Don
t Care
Don
t Care
Don
t Care
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