Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
93
PM2329 ClassiPI Network Classification Processor Datasheet
Rule memory for each PM2329 device is local to it and contained on-chip, i.e., the processor sees as many
rule memory blocks as the number of PM2329 devices in the cascade with their own associated address
pointers and indirect data registers for access. While various PM2329 devices have separate E-RAMs
attached to them, they present a unified view (a common block of memory) to the processor accessed via a
common address pointer and a distributed yet common set of indirect data register set.
Additionally, the E-RAM access mechanism supports the Auto Increment Mode Select bit as explained in
the E-RAM Indirect Command Register section. It also has a depth Level field (part of the E-RAM
address) as explained in the E-RAM Indirect Address Register section.
As long as the processor manages E-RAM Write and Read operations using the RSR handshake, the
processor can perform these operations at any time even when OC sequencing is in progress--the read or
write operation will take place arbitrated by PM2329 control logic. The software must ensure coherency of
OC operation vs. the access operation. Also, it must manage multiple E-RAM updates using the RSR bit.
Unlike RIDR (Rule Memory access mechanism) read operation, reading the EIDR set as the trigger word
will always cause an E-RAM read operation regardless of whether the EICR, EIAR or EIDR were written
to or not since the last ERAM read operation.