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參數(shù)資料
| 型號： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 59/162頁 |
| 文件大?。?/td> | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
62
PM2329 ClassiPI Network Classification Processor Datasheet
The multi-channel operation of the PM2329 is enabled by setting a bit in the Operation Control Register to
enable the multi-channel mode. Note that packet data transfer when multi-channel mode is enabled must
be done using processor cycles. Packet Source (DMA) transfers are not supported in this case.
In the multi-channel mode, the 8 KB input buffer is organized as 32 segments of 256 bytes each. Packet
Input Buffer Registers for each segment are provided so that the external processor(s) may write to any
segment (based on the context that is writing the packet). Similarly, the 128 entry results FIFO gets
organized into 32 segments of 4 entries each. The combination of the input buffer and the associated results
segment defines a channel. These channels are numbered 0 through 31. Consequently, 32 simultaneous
channels can co-exist and be used by 32 independent tasks/contexts. The registers used to load the packet,
retrieve results, and check the packet processing status are organized in a per-channel fashion into channel-
oriented register groups. This allows multiple contexts on the external processor to access their channel
registers simply by using the appropriate base address for that channel group.
The PM2329 processes the packets in the order in which packet transfers complete. Results from packet
processing are then sent to the appropriate segment in the Results FIFO. The results for a channel are made
available through an OC Results FIFO Read Port for each channel.
The SCHNUM[4:0] and SCHSTB pins on the PM2329 provide the required support to accomplish a
hardware-based handshake between the PM2329 and the processor. For processors equipped to handle
such handshake signals, this interface awakens a context whenever its packet processing results are ready.
If the processor does not implement this interface, a Channel Status Register can be read by any context to
determine the status of the Packet Input Buffers and result FIFOs for that channel.
Concatenation of segments is supported to allow any channel to transfer a packet larger than 256 bytes or
to accumulate more than 4 results. This is accomplished using the Channel Assignment Register. This
allows any number of adjacent channels to be concatenated to work as a single larger channel. When 4
channels are concatenated, for example, the Packet Input Buffer will appear to be 1 KB in length and the
OC Results will appear to be a 16 deep FIFO.
3.1.4 Channel Input, Output and Status Mechanism
Each channel (0 through 31) has its pre-assigned packet input buffer available for loading after reset and
after the previously loaded packet has been processed. Since the write ports associated with the packet
input buffers share the processor bus, only one of them can be written to at a time; however, they can be
loaded in an interleaved fashion. Once a packet has been loaded by a context, the context must wait until
the processing for this packet is complete as indicated by OC Sequence Terminated bit, before loading the
next packet for its assigned channel.
The diagram below shows the operation of status bits used for Packet input and Result output.
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