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| 型號(hào)： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 72/162頁(yè) |
| 文件大?。?/td> | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
75
PM2329 ClassiPI Network Classification Processor Datasheet
Destination columns show the PM2329 devices participating in the read or write operations, respectively.
CID n indicates the address device n responds to the access, CID # or #~# indicates the device with the
specified ID responds to the access. In the address column, the addresses for local registers are shown as
‘
nNNN
’
(for example,
‘
n000
’
). To access the register of a specific PM2329 device in the cascade,
substitute a number from 0 to 7 for
‘
n
’
, depending on the device to be accessed. For example, in a single
PM2329 system or to access the Primary PM2329 in a cascade,
‘
n
’
would equal
‘
0
’
.
PM2329 registers generally fall into one of three categories:
Setup and Control,
Packet Input, and
Result Output.
They must be written to or read from in specified sequences and at appropriate times to ensure proper
device operation. For example, improperly sequenced or ill-timed modification of setup and control
registers when a packet is being processed by the device can result in operation failure, the new value
being ignored, or some other unpredictable behavior.
All PM2329 registers are 64-bit locations; however, they can be accessed either in 64-bit or 32-bit mode. If
the processor executes a 64-bit access using a register address specified in Table 17, it will accesses the
entire register. If the processor executes a 32-bit access using the same address, it will access the upper half
of the register (bits 63:32). To access the lower half (bits 31:0) of the register using 32-bit access, the value
‘
04h
’
should be added to the address specified in Table 17. Bits in every register are aligned toward bit 0
(that is, right-aligned), so for all registers with bits in the lower half only, 32-bit accesses should be at the
address+04h location.
Figure 25 provides a graphical representation of the address space.
17
Alternate OC Conductor
Register
Channel Register Block Base
Addresses
R/W
Global
CID 0
CID 0~7
8270h
18
See Table 4.2 for further details
See
Table
19
Global
See Table 19
See Table 19
8400h - 8600h,
C000h - CFFFh,
D000h - D7FFh,
E000h - FFFFh
Table 17
PM2329 Register Memory Map
#
Register Name
Mode
Local
or
Global
Source
(Processor
Read)
Destination
(Processor
Write)
Address
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