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    參數(shù)資料
    型號(hào): PM2329
    英文描述: Telecommunication IC
    中文描述: 通信集成電路
    文件頁數(shù): 40/162頁
    文件大?。?/td> 1581K
    代理商: PM2329
    Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
    Internal Use
    Document ID: PMC-2010146, Issue 4
    43
    PM2329 ClassiPI Network Classification Processor Datasheet
    Figure 5 System Interface Register Timing Diagram (SyncBurst)
    A Write cycle occurs as follows:
    1.
    SA[15:3], and SD[63:32] and SD[31:0] (as required) are driven by the processor. SCE0* and
    SCE1* are asserted low and SCE2 is asserted high by the processor. One or both of SWHE* and
    SWLE* are asserted low to indicate the 32-bit lanes on which the write should occur.
    2.
    On the next rising edge of SCLK, the write cycle occurs.
    3.
    In case of back-to-back writes, the next write occurs on the next clock edge.
    Register Read and Write Timing, SyncBurst Mode
    For Reads (address and control cycle), either...
    1) SR/W* should be high and SWHE* and SWLE* are don
    t care (shown), or
    2) SR/W* should be low and SWHE* and SWLE* should be high (not shown).
    SCLK
    SA[15:3]
    SD[63:0]
    SCE0*/
    SCE1*
    SCE2
    SOE*
    SRW*
    SWHE*
    SWLE*
    WA1
    WA2
    RA1
    RA2
    WA3
    WA4
    WD1
    WD2
    Undefined
    RD1
    RD2
    WD3
    WD4
    Don
    t Care
    Don
    t Care
    Write Cycles
    Write Cycles
    Read Cycles
    PSCC
    PSPD
    PSEOP
    Don
    t Care
    Don
    t Care
    Don
    t Care
    Don
    t Care
    Don
    t Care
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