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參數(shù)資料
| 型號(hào)： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 39/162頁(yè) |
| 文件大?。?/td> | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
42
PM2329 ClassiPI Network Classification Processor Datasheet
The diagram below shows the bypass mechanism for on-chip PLLs. When PLLA is bypassed,
PLLACTL[1:0] signals must still be tied appropriately to specify the desired SCLK vs. ACLK clock ratio.
Figure 4 On-Chip PLL Bypass Mechanism
2.4.1.2 Processor Bus Cycles
The PM2329 interface to the processor has been designed to appear like a synchronous pipelined SRAM.
Two types of bus timings are supported: SyncBurst and ZBT. The block read or block write throughput is
the same for SyncBurst and ZBT timings. However, ZBT timings allow greater throughput for random
read and write operations. The basic signals involved in a processor access are: SD[63:0], SA[15:3],
SWE*, SOE*, SWHE*, SWLE*, SCE0*, SCE1* and SCE2.
In addition to the SCE0* signal, two additional chip enable signals--SCE1* and SCE2--are provided, for a
total of two active low and one active high chip enable signals. This allows the PM2329 to interface with
external processor at high speed, without the need of any external glue logic for address decode. For
systems that do not require multiple chip enable signals, the (one or two) unused SCEn signals can be
permanently tied to their active state.
2.4.1.2.1 SyncBurst Bus Cycles
Processor accesses may be either write cycles or read cycles. The write cycle is conducted in a single clock
period, whereas the read takes 3 clock periods. The PM2329 supports contiguous or back-to-back transfers
for both read and write operations.
SYS
PLL
DISABLE
PLLSBYPS
SCLK
0
1
Internal SCLK
ECLK
ACLK
PLL
DISABLE
PLLABYPS
ACLKIN
0
1
Internal
ACLK
PLLACTL[1:0]
TESTMODE
SCLKOUT
/4
ACLKOUT
0
1
SFBCK
0
1
AFBCK/4
P
P
T
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Normal
Bypass SCLK
Bypass ACLK
Bypass both
Test use
Function
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