參數(shù)資料
型號: PM2329
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 22/162頁
文件大小: 1581K
代理商: PM2329
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
Internal Use
Document ID: PMC-2010146, Issue 4
25
PM2329 ClassiPI Network Classification Processor Datasheet
PLLACTL[1:0]
P2
P3
2
I
PLLA Control
These pins select an internal ACLK clock of 4xSCLK,
3xSCLK, 2xSCLK or 1xSCLK. These control signals
must be tied high or low as required and must not
change during the operation of the PM2329.
If Nominal CVDD = 1.5V
00: 4x for SCLK < 50 MHz
01: 3x for SCLK < 66 MHz
10: 2x for SCLK < 100 MHz
11: 1x for SCLK < 100 MHz (for reduced power
application)
If Nominal CVDD = 1.6V
00: 4x for SCLK < 58 MHz
01: 3x for SCLK < 77 MHz
10: 2x for SCLK < 116 MHz
11: 1x for SCLK < 116 MHz (for reduced power
application)
These control signals must be tied appropriately, even
when the PLLA is bypassed.
PLLA Bypass
PLLABYPS
N2
1
I
During normal device operation, this signal must be
grounded and its state must not be changed during
operation of the PM2329.
In order to bypass the internal PLLA, this signal must be
forced high and the ACLK clock signal supplied on the
ACLKIN pin from an external source.
Table 1
Timing and Common Control Signals
Signal Name
Ball # Size
I/O
Description
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