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參數(shù)資料
| 型號： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 114/162頁 |
| 文件大?。?/td> | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
117
PM2329 ClassiPI Network Classification Processor Datasheet
words will be written to Base 3 +0E0h, +0E8h and +0F0h and the EOP word will be written to +0F8h, as
required.
In case the transfer Direction is 1, block moves can still be used; however, the EOP D1 must be written at a
separate non-contiguous address using a separate write cycle.
When channels are concatenated, the EOP address of the concatenated channel is the EOP address of the
highest channel in the concatenated set. For example, if channels 0 through 3 are concatenated to form a
1K deep channel, address +000 through +3F0 act as non-EOP addresses and +3F8 will be the EOP D0
adderss.
If automatic header extraction is disabled for this packet, then the first two 64-bit words (or first four 32-bit
words) in the packet can contain pre-extracted header data for use with policies which inspect the packet
header. If the pre-extracted header is to be compatible with the FEE extracted header (so that the same
classification rules
may be applied to this packet), these words must be formatted as follows.
The Flags field is further defined as follows:
The Packet Input Buffer is organized as 32 segments of 256 bytes each. Regardless of the state of Enable
Multi-Channel Mode bit, packets are stored starting at segment boundaries.
In the single channel mode, up to 32 packets of up to 256 bytes each can be transferred into the Packet
Input Buffer. Note that if a packet exceeds 256 bytes, the next byte is placed in the next segment and the
full 256-byte segment is also assigned to this packet. As an example, if the processor downloads a 264-byte
packet, only 30 additional packets up to 256 bytes each can be input.
In the multi-channel mode, up to 32 packets of 256 bytes each can be input. For further information
regarding packet input in multi-channel mode, refer to the Channel Assignment register description.
1st Word
63.............................................32
SIP
63................48
SP
31................................................0
DIP
31.........24
Protocol
Flags
2nd Word
47.................32
DP
23...20
19...............0
(Reserved)
Bit Position
23
22
21
20
Flag
Reserved; set to 0
a
ACK
SYN
FIN
a. Regardless of the source of the header information (pre-extracted or on-
chip extraction), the DIR bit is always derived as described in the
Direction Specifier control bit description in Operation Control Register
and inserted into this bit position in the internal header holding register.
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