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參數(shù)資料
| 型號： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 112/162頁 |
| 文件大?。?/td> | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
115
PM2329 ClassiPI Network Classification Processor Datasheet
4.2.2.18 Packet Buffer Input Register
(PBIR; Base 3 +00h, +08h,... +0E8h, +0F0h)
(PBIR, EOPD0; Base 3 +0F8h)
(PBIR, EOPD1; Base 0 +08h)
Channel Register
Access Mode: Write Only, Global
The external processor or the Packet Source device (or DMA Source) writes to this register to transfer the
packet data to the PM2329. Data written to this register fills the corresponding Packet Input Buffer.
The PM2329 supports two mechanisms to load the Packet Input Buffer. A FIFO-like load mechanism
similar to the PM2328, and an SRAM-like write mechanism to support DMA capabilities of some network
processors. While the Packet Input Buffer itself is a FIFO (in the data path between the system interface
and the Field Extraction Engine) that supports a single write port type addressing, the FIFO address logic
also supports an SRAM like addressing mechanism. The last transfer of the packet that indicates the end of
packet and also packet direction information must always be done to one of two separate EOP addresses.
When utilizing SRAM like addressing mechanism, the last transfer address is arranged to indicate EOP-
Direction 0 in an efficient manner.
For each channel (as determined by the base address), multiple address offsets are assigned to this register.
Depending on the offset, direction and end-of-packet information are communicated to the PM2329. This
offset assignment is as follows:
All data for the packet must be written to the PBIR address except the last write, which is written to the
appropriate EOP (EOPD0 or EOPD1) address. For the last packet data write, valid data must be left
justified and the rest of the word padded by nulls.
The tables below shows the writes to be performed to transfer 64-, 96- and 128-bit packets in 32- or 64-bit
modes. This can be used as a guideline for other packet sizes. Also, this table shows the write cycles
Register
PBIR
Address
(64-bit
Write)
Base 3 +00H,
+08H,...,
+0E8H,
+0F0H
Address
(32-bit
Write)
Base 3 +00H,
+04H,
+08H,...,
+0F0H,
+0F4H
Base 3 +0FCH
Direction
EOP
X
No
PBIR
EOPD0
PBIR
EOPD1
Base 3 +0F8H
0
Yes
Base 0 +08H
Base 0 +0CH
1
Yes
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