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參數(shù)資料
| 型號： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 38/162頁 |
| 文件大小： | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
41
PM2329 ClassiPI Network Classification Processor Datasheet
2.4 Interface Description
2.4.1 System Interface
The System Interface is a general-purpose, 64-bit synchronous bus interface, which can optionally be
configured as a 32-bit interface by holding the SDWIDTH64 pin low during reset. The PM2329
’
s ability to
perform wire-speed operations at Gigabit rates is dependent on the speed of data transfer over this
interface. In general, data transfer speed will be halved when the system interface is configured for 32-bit
wide data.
The System Interface is used by:
1.
The processor to access the registers and Rules Memory of the PM2329 and the Extended RAM
locations.
2.
The packet source (or DMA source) to load packets (or packet data) to the PM2329.
The PM2329 is designed to interface to the processor as well as the packet source (configured as a DMA
device) for packet transfer without any additional logic. In case a packet source (DMA) is not present, the
processor can perform packet transfer.
2.4.1.1 Clock Frequency
The system clock input signal (SCLK) controls the timing of the synchronous system bus signals; address,
data and control signal timings are all referenced to the system clock.
The Cascade and E-RAM interfaces also run at the SCLK frequency and are synchronous to SCLK.
However, in order to provide improved timing on the E-RAM interface, the PM2329 generates the
ECLKOUT signal for the external E-RAM devices.
In a lightly loaded system bus with up to two cascaded PM2329 devices and associated E-RAMs, the
SCLK frequency may be up to 100MHz. When running at 116MHz SCLK frequency, only a single
PM2329 device operation is recommended. Factors such as bus loading must be considered in determining
the SCLK frequency. When operating the device at 100 MHz or 116MHz, it is recommended that all high-
speed signals should be source- and destination-terminated, to minimize problems due to ground bounce or
ringing. Low inductance terminating resistors in the range of 17 to 33 ohms are recommended.
In applications with 3 or more cascaded PM2329 devices and associated E-RAMs, the SCLK frequency
should be less than the rated maximum clock input. The actual frequency used in these systems should be
appropriately selected in order to achieve a balance of interface speed and the maximum throughput from
the PSE logic.
The Policy Search Engine PSE of the PM2329 can run at a frequency of up to 232 MHz regardless of the
number of devices in the cascade. It is clocked by an internally generated PSE clock, which is derived from
the externally supplied SCLK using an on-chip PLL. The internal PSE clock is derived by multiplying the
SCLK by a multiplier of 1x, 2x, 3x or 4x. The multiplier value is sampled at reset by the PM2329 on the
PLLCTL[1:0] pins.
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