Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
81
PM2329 ClassiPI Network Classification Processor Datasheet
SCH Timing Mode Select
This bit controls the clock frequency at which the SCHSTB and SCHNUM operate. This bit can be
configured as follows:
0:
SCHSTB and SCHNUM[] operate at the same frequency as SCLK.
1:
SCHTB and SCHNUM[] operate at half the frequency of SCLK.
Device Revision Number
This field indicates the revision number of the device. For the PM2329-A1, this field is hardwired to
04h.
PLLA Multiplier
These two bits indicate the value of the PLLA multiplier sensed at reset. For a description of this field
’
s
value and the corresponding PLLA multiplier, see the PLLACTRL[1:0] description in Chapter 2,
Section 2.2 Pin Description Table.
Cascade Mask
These bits specify which of the chips in the cascade were detected via handshake using COCDOUT
lines during reset. The external processor can read this field to determine the number of PM2329
devices in the cascade.
ZBT Enable
This bit indicates the value of ZBT_MODE signal sampled at reset. If this bit is
‘
0
’
, a low level was
sensed at reset and the PM2329 system interface is configured for SyncBurst mode. If this bit is
‘
1
’
, a
high level was sensed at reset and the PM2329 system interface is configured for ZBT operation.
System Interface Bus Width
This bit indicates the value of SD_WIDTH signal sampled at reset. If this bit is
‘
0
’
, a low level was
sensed at reset and the PM2329 is configured for 32-bit mode. If this bit is
‘
1
’
, a high level was sensed
at reset and the PM2329 is configured for 64-bit mode.
CID Number
These 3 bits return the PM2329 ID number for that particular PM2329 as set up by the CID[2:0] inputs
sensed at reset.