Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
88
PM2329 ClassiPI Network Classification Processor Datasheet
For sequential write operation, the processor must perform the following steps.
1.
Check the RSR bit is set to
‘
1
’
to ensure the previous memory transaction is complete.
2.
Set up RICR with the Data Enable and Trigger fields, and the auto-increment bit set to
‘
1
’
.
3.
Set up the RIAR with the start address of the locations to be written.
4.
Write the RIDR, the trigger word should be written last.
5.
Wait for RSR bit to be set to
‘
1
’
Repeat steps 5 and 6 to write the rest of the memory block.
4.2.2.5 OC Descriptors (OCD; n400h, n408h...n7F0h, n7F8h)
Access Mode: Read/Write, Local
OC Descriptor
Each OCD occupies two consecutive 64-bit locations: Upper OCD [n] and Lower OCD [n], where n is the
OC Descriptor Index. OCDI. Since each full OC Descriptor is 96 bits wide spanning two 64-bit register
locations or three 32-bit register locations, the user must exercise caution when updating the OC
Descriptor while an OC that uses this OC Descriptor is executing. OC Descriptors can be updated without
any side effects when:
1) no OC execution is in progress, or
2) if the OC Descriptor to be updated will not be used by the current OC that is executing.
Upper
OC Descriptor
Bit
Range
63
62:61
60
59:54
53:48
47:32
31:29
28:16
15
14:11
12:0
Size
1
2
1
6
6
16
3
13
1
2
13
Name
Value after
Reset
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
OC Descriptor Valid
OC Type
Enable Multi-hit
Row Start Number
Row End Number
Column Select Enable
(Reserved)
Pattern Search Start Offset
Pattern Search Direction
(Reserved)
Pattern Search Count