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參數(shù)資料
| 型號： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 41/162頁 |
| 文件大小： | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
44
PM2329 ClassiPI Network Classification Processor Datasheet
A Read cycle occurs as follows:
1.
SA[15:3] is driven by the processor. SCE0* and SCE1* are asserted low and SCE2 is asserted
high by the processor. PM2329 latches this state on the first rising edge of clock and starts the read
cycle internally. (Note: If SRW* is driven low and SWHE* and SWLE* are high, then the
PM2329 treats this as a read cycle in SyncBurst mode to be compatible with SyncBurst SRAM
specification. In ZBT mode, this case is treated as no operation.)
2.
On the second rising edge, the PM2329 internally fetches the data to be read. The processor must
drive SOE* before the second rising edge. This causes the PM2329 output buffers to be enabled
and drive the read data onto the System bus. Keeping SOE* low through the third rising edge will
allow the processor to latch the data on this edge.
3.
In case of back-to-back reads, the next cycle address and control signals can be asserted after the
first rising edge and PM2329 will latch this state on the second rising edge in a pipelined fashion.
Thus, read data can be transferred on every cycle.
Note:
SRW* should be tied low for SyncBurst mode.
2.4.1.2.2 ZBT Bus Cycles
In the ZBT mode, both the read and write cycles are pipelined. The read cycle is the same as the normal
(SyncBurst) mode. (Except for the case stated above: if SRW* is driven low and SWHE* and SWLE* are
high in ZBT mode, the PM2329 treats the case as a
‘
no operation
’
.). The write cycle is conducted in 3
clock periods, just like the read. The ZBT mode thus supports contiguous or back-to-back transfers on both
read and write or interleaved read/write/read cycles. The ZBT operation results in greater available bus
bandwidth when random reads/writes are performed.
In a write cycle in ZBT mode, the processor drives the SA[15:3] on the first rising edge. It also drives
SRW* low to indicate a write cycle and asserts SCE0*, SCE1* and SCE2 signals on the first rising edge.
One or both of SWHE* and SWLE* are asserted low on the first rising edge to indicate the 32-bit lanes on
which the write should occur. Finally, the processor asserts write data SD[63:32] and SD[31:0] (as
required) on the third rising edge.
There is an important consideration when the PM2329 is used in ZBT mode: If a register is written in cycle
1, its value will only be available for read during bus cycle 4. That is, read cycles performed in bus cycles
2 and 3 will return the old register value
.
Similarly, if a write to register Q is expected to cause a change in
the value of register R, then the new value of register R will only be visible when read at least 2 clock
cycles after register Q has been written.
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