參數(shù)資料
型號(hào): PM2329
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 74/162頁
文件大?。?/td> 1581K
代理商: PM2329
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
Internal Use
Document ID: PMC-2010146, Issue 4
77
PM2329 ClassiPI Network Classification Processor Datasheet
Table 18 summarizes the address assignments. Note that all reserved bits must be written with zeroes.
When read, reserved bit values returned will be invalid and must be masked out by the processor.
Table 18 shows the Channel Register Block base addresses for each of the 32 channels. Note that each
channel has four blocks of registers at four separate base addresses. Relative to the base addresses,
individual channel registers can be accessed as shown in Table 19 below.
Table 18
Channel Register Block Base Addresses
Base 0
Base 1
Base 2
Base 3
Channel
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CSR
and
EOP-D1
8400h
8410h
8420h
8430h
8440h
8450h
8460h
8470h
8480h
8490h
84A0h
84B0h
84C0h
84D0h
84E0h
84F0h
8500h
8510h
8520h
8530h
8540h
8550h
8560h
8570h
8580h
8590h
85A0h
85B0h
85C0h
85D0h
85E0h
85F0h
OC Result
and
Data Result 0/
1
C000h
C080h
C100h
C180h
C200h
C280h
C300h
C380h
C400h
C480h
C500h
C580h
C600h
C680h
C700h
C780h
C800h
C880h
C900h
C980h
CA00h
CA80h
CB00h
CB80h
CC00h
CC80h
CD00h
CD80h
CE00h
CE80h
CF00h
CF80h
Data Result 2/
3, Data Result
4/5,
and
Data
Result 6
D000h
D020h
D040h
D060h
D080h
D0A0h
D0C0h
D0E0h
D100h
D120h
D140h
D160h
D180h
D1A0h
D1C0h
D1E0h
D200h
D220h
D240h
D260h
D280h
D2A0h
D2C0h
D2E0h
D300h
D320h
D340h
D360h
D380h
D3A0h
D3C0h
D3E0h
Packet Input
and
EOP D0
E000h
E100h
E200h
E300h
E400h
E500h
E600h
E700h
E800h
E900h
EA00h
EB00h
EC00h
ED00h
EE00h
EF00h
F000h
F100h
F200h
F300h
F400h
F500h
F600h
F700h
F800h
F900h
FA00h
FB00h
FC00h
FD00h
FE00h
FF00h
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