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Document ID: PMC-2010146, Issue 4
80
PM2329 ClassiPI Network Classification Processor Datasheet
4.2.2.1 Local Configuration Register (LCR; n000h)
Access Mode: Read/Write, Local
This register returns bits that indicate the hardware configuration of the PM2329. All bits, except bit 62,
are read-only.
BIST Result
This bit indicates the result of the last BIST run. It should be read after the BIST operation has been
enabled (BIST Enable/Status LCR[62] is written with 1) and the BIST execution is complete (indicated
by BIST Enable/Status LCR[62] = 0). When sampled, if this bit LCR[63] is 0, then the BIST failed; if
this bit is 1, then the BIST passed.
This bit is set to 0 when BIST Enable/Status LCR[62] is written with 1.
This bit is 0 after reset.
BIST Enable/Status
This bit controls the operation of the on-chip BIST facility for internal RAM blocks. Writing a 1 to this
bit activates the BIST operation inside the device. This bit will stay 1 as long as the BIST operation is in
progress, and it will become 0 when the BIST execution is complete.
After the BIST sequence is completed successfully, the following on-chip resources are initialized:
Rule Memory:NO MATCH
OCDs: INVALID OC
Since all rules are loaded with NO MATCH and all OCDs are loaded with INVALID OCs, control
software need not initialize unused rules and OCDs.
This bit is 0 after reset.
Bit
Range
63
62
61:59
58
57:53
52:32
31:24
23:18
17:16
15:8
7
6
5
4:2
1:0
Size
1
1
3
1
5
21
8
6
2
8
1
1
1
3
2
Name
Value after
Reset
BIST Result
BIST Enable/Status
(Reserved)
SCH Timing Mode Select
(Reserved)
(Reserved)
Device Revision Number
(Reserved)
PLL Multiplier
Cascade Mask
(Reserved)
ZBT Enable
System I/F Bus Width
CID Number
(Reserved)
0
0
Undefined
0
Undefined
00 0000h
04h
Undefined
PLL Multiplier
Cascade Mask
Undefined
ZBT Mode
Sys I/F Bus Width
CID#
Undefined