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參數(shù)資料
| 型號： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁數(shù)： | 84/160頁 |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
84
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
15.2.12.4 SI, the Serial Interrupt Flag
SI = “1”: When the SI flag is set, then, if the EA and ES1
(interrupt enable register) bits are also set, a serial
interrupt is requested. SI is set by hardware when one of
25ofthe26possibleSIO1statesisentered.Theonlystate
that does not cause SI to be set is state F8H, which
indicates that no relevant state information is available.
WhileSIisset,thelowperiodoftheserialclockontheSCL
line is stretched, and the serial transfer is suspended. A
high level on the SCL line is unaffected by the serial
interrupt flag. SI must be reset by software.
SI = 0: When the SI flag is reset, no serial interrupt is
requested, and there is no stretching of the serial clock on
the SCL line.
15.2.12.5 AA, the Assert Acknowledge flag
AA = “1”: If the AA flag is set, an acknowledge (low level to
SDA) will be returned during the acknowledge clock pulse
on the SCL line when:
The “own slave address” has been received
The general call address has been received while the
general call bit (GC) in S1ADR is set
A data byte has been received while SIO1 is in the
master receiver mode
A data byte has been received while SIO1 is in the
addressed slave receiver mode
AA = “0”: if the AA flag is reset, a not acknowledge (high
level to SDA) will be returned during the acknowledge
clock pulse on SCL when:
A data has been received while SIO1 is in the master
receiver mode
A data byte has been received while SIO1 is in the
addressed slave receiver mode
When SIO1 is in the addressed slave transmitter mode,
state C8H will be entered after the last serial is transmitted
(see Figure 40). When SI is cleared, SIO1 leaves state
C8H, enters the not addressed slave receiver mode, and
the SDA line remains at a high level. In state C8H, the AA
flag can be set again for future address recognition.
When SIO1 is in the not addressed slave mode, its own
slave address and the general call address are ignored.
Consequently, no acknowledge is returned, and a serial
interrupt is not requested. Thus, SIO1 can be temporarily
released from the I
2
C bus while the bus status is
monitored. While SIO1 is released from the bus, START
and STOP conditions are detected, and serial data is
shiftedin.Addressrecognitioncanberesumedat anytime
by setting the AA flag. If the AA flag is set when the parts
own slave address or the general call address has been
partly received, the address will be recognized at the end
of the byte transmission.
15.2.12.6 CR0, CR1, and CR2, the Clock Rate Bits
These three bits determine the serial clock frequency
when SIO1 is in a master mode. The various serial rates
are shown in Table 57.
A 12.5 kHz bit rate may be used by devices that interface
to the I
2
C bus via standard I/O port lines which are
software driven and slow. 100kHz is usually the maximum
bit rate and can be derived from a 16 MHz, 12 MHz, or a
6 MHz oscillator. A variable bit rate (0.5 kHz to 62.5 kHz)
may also be used if Timer 1 is not required for any other
purpose while SIO1 is in a master mode.
The frequencies shown in Table 57 are unimportant when
SIO1 is in a slave mode. In the slave modes, SIO1 will
automatically synchronize with any clock frequency up to
100 kHz.
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