參數(shù)資料
型號: P8XC591
廠商: NXP Semiconductors N.V.
英文描述: HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述: 單芯片8 - CAN控制器位微控制器
文件頁數(shù): 27/160頁
文件大?。?/td> 601K
代理商: P8XC591
2000 Jul 26
27
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
12.3
Communication between PeliCAN controller
and CPU
A 80C51 CPU Interface connects the PeliCAN to the
internal bus of an 80C51 microcontroller. Special Function
Registers, allows a smart and fast access to the PeliCAN
registersandRAMarea.Becauseofthebigaddressrange
to be supported, an indirect pointer based addressing is
included allowing a fast register access with address
autoincrement mode. This reduces the needed number of
Special Function Registers to an amount of 5.
Five Special Function Registers (SFRs)
Register address generation in auto-increment mode
Access to the complete address range of the PeliCAN
Fig.11 CPU to CAN Interfacing.
handbook, full pagewidth
MHI020
data
80C51
CORE
write
read
SFRs
PeliCAN
address
CANDAT
CANADR
INTERFACE
CAN CONTROLLER
CANSTA
CANCON
CANMOD
12.3.1
S
PECIAL
F
UNCTION
R
EGISTERS
Via the five Special Function Registers CANADR,
CANDAT, CANMOD, CANSTA and CANCON the CPU
has access to the PeliCAN Block. Note that CANCON and
CANSTA have different registers mapped depending on
the direction of the access.
The PeliCAN registers may be accessed in two different
ways. The most important registers, which should support
software polling or are controlling major CAN functions are
accessible directly as separate SFRs. Other parts of the
PeliCAN Block are accessible using an indirect pointer
mechanism. In order to achieve a high data throughput
even if the indirect access is used, an address
auto-increment feature is included here.
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