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參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 80/160頁(yè) |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
80
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
15.2.10.1 The Address Register, S1ADR
The CPU can read from and write to this 8-bit, directly
addressable SFR. S1ADR is not affected by the SIO1
hardware. The contents of this register are irrelevant when
SIO1 is in a master mode. In the slave modes, the seven
most significant bits must be loaded with the
microcontrollers own slave address, and, if the least
significant bit is set, the general call address (00H) is
recognized; otherwise it is ignored.
Themostsignificantbitcorrespondstothefirstbitreceived
from the I
2
C bus after a start condition. A logic 1 in S1ADR
corresponds to a high level on the I
2
C bus, and a logic 0
corresponds to a low level on the bus.
Table 51
Address Register S1ADR (address DBH)
Table 52
Description of S1ADR (DBH) bits
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
GC
BIT
SYMBOL
DESCRIPTION
7 to 1
0
X
Own slave address.
0 = general call address is not recognized.
1 = general call address is recognized.
GC
15.2.11 T
HE
D
ATA
R
EGISTER
, S1DAT
S1DAT contains a byte of serial data to be transmitted or
a byte which has just been received. The CPU can read
from and write to this 8-bit, directly addressable SFR while
it is not in the process of shifting a byte. This occurs when
SIO1 is in a defined state and the serial interrupt flag is set.
Data in S1DAT remains stable as long as SI is set. Data in
S1DAT is always shifted from right to left: the first bit to be
transmitted is the MSB (bit 7), and, after a byte has been
received, the first bit of received data is located at the MSB
of S1DAT. While data is being shifted out, data on the bus
is simultaneously being shifted in; S1DAT always contains
the last data byte present on the bus. Thus, in the event of
lost arbitration, the transition from master transmitter to
slave receiver is made with the correct data in S1DAT.
S1DAT and the ACK flag form a 9-bit shift register which
shifts in or shifts out an 8-bit byte, followed by an
acknowledge bit. The ACK flag is controlled by the SIO1
hardwareand cannotbeaccessedbytheCPU. Serialdata
is shifted through the ACK flag into S1DAT on the rising
edges of serial clock pulses on the SCL line. When a byte
has been shifted into S1DAT, the serial data is available in
S1DAT, and the acknowledge bit is returned by the control
logic during the ninth clock pulse. Serial data is shifted out
from S1DAT via a buffer (BSD7) on the falling edges of
clock pulses on the SCL line.
When the CPU writes to S1DAT, BSD7 is loaded with the
content of S1DAT.7, which is the first bit to be transmitted
to the SDA line (see Figure 36). After nine serial clock
pulses, the eight bits in S1DAT will have been transmitted
to the SDA line, and the acknowledge bit will be present in
ACK. Note that the eight transmitted bits are shifted back
into S1DAT.
Table 53
Address Register S1DAT (address DAH)
Table 54
Description of S1DAT (DAH) bits
7
6
5
4
3
2
1
0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
BIT
SYMBOL
DESCRIPTION
7 to 0
SD7 to SD0
Eight bits to be transmitted or just received. A logic 1 in S1DAT corresponds to a high
level on the I
2
C bus, and a logic 0 corresponds to a low level on the bus. Serial data
shifts through S1DAT from right to left. Figure 35 shows how data in S1DAT is serially
transferred to and from the SDA line.
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