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參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 78/160頁(yè) |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
78
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
15.2.5
A
RBITRATION AND
S
YNCHRONIZATION
L
OGIC
Inthemastertransmittermode,thearbitrationlogicchecks
that every transmitted logic 1 actually appears as a logic 1
on the I
2
C bus. If another device on the bus overrules a
logic 1 and pulls the SDA line low, arbitration is lost, and
SIO1 immediately changes from master transmitter to
slave receiver. SIO1 will continue to output clock pulses
(on SCL) until transmission of the current serial byte is
complete.
Arbitration may also be lost in the master receiver mode.
Loss of arbitration in this mode can only occur while SIO1
is returning a not acknowledge: (logic 1) to the bus.
Arbitration is lost when another device on the bus pulls this
signal LOW. Since this can occur only at the end of a serial
byte, SIO1 generates no further clock pulses. Figure 33
shows the arbitration procedure.
The synchronization logic will synchronize the serial clock
generator with the clock pulses on the SCL line from
another device. If two or more master devices generate
clock pulses, the mark duration is determined by the
device that generates the shortest marks, and the space
duration is determined by the device that generates the
longest spaces. Figure 34 shows the synchronization
procedure.
A slave may stretch the space duration to slow down the
bus master. The space duration may also be stretched for
handshaking purposes. This can be done after each bit or
after a complete byte transfer. SIO1 will stretch the SCL
space duration after a byte has been transmitted or
received and the acknowledge bit has been transferred.
The serial interrupt flag (SI) is set, and the stretching
continues until the serial interrupt flag is cleared.
Fig.33 Arbitration Procedure.
handbook, full pagewidth
MHI034
SDA
SCL
1
2
3
4
8
9
ACK
(2)
(1)
(1)
(3)
(1) Another device transmits identical serial data.
(2) Another device overrules a logic 1 (dotted line) transmitted by SIO1 (master) by pulling the SDA line low. Arbitration is lost,
and SIO1 enters the slave receiver mode.
(3) SIO1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted. SIO1 will not
generate clock pulses for the next byte. Data on SDA originates from the new master once it has won arbitration.
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