參數(shù)資料
型號: P8XC591
廠商: NXP Semiconductors N.V.
英文描述: HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述: 單芯片8 - CAN控制器位微控制器
文件頁數(shù): 140/160頁
文件大小: 601K
代理商: P8XC591
2000 Jul 26
140
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
Table 111
Description of the mnemonics in the Instruction set
MNEMONIC
DESCRIPTION
Data addressing modes
Rr
direct
@Ri
#data
#data 16
bit
addr16
Working register R0-R7.
128 internal RAM locations and any special function register (SFR).
Indirect internal RAM location addressed by register R0 or R1 of the actual register bank.
8-bit constant included in instruction.
16-bit constant included as bytes 2 and 3 of instruction.
Direct addressed bit in internal RAM or SFR.
16-bit destination address. Used by LCALL and LJMP.
The branch will be anywhere within the 64 Kbytes Program Memory address space.
11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 Kbytes
page of Program Memory as the first byte of the following instruction.
Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps.
Range is
128 to +127 bytes relative to first byte of the following instruction.
addr11
rel
Hexadecimal opcode cross-reference
*
8, 9, A, B, C, D, E, F.
1, 3, 5, 7, 9, B, D, F.
0, 2, 4, 6, 8, A, C, E.
22.1
Addressing Modes
Most instructions have a ‘destination, source’ field that
specifies the data type, addressing modes and operands
involved. For all these instructions, except for MOVs, the
destination operand is also the source operand
(e.g. ADD A,R7).
There are five kinds of addressing modes:
Register Addressing
– R0 - R7 (4 banks)
– A,B,C (bit), AB (2 bytes), DPTR (double byte)
Direct Addressing
– lower 128 bytes of internal Main RAM (including the
4 R0-R7 register banks)
– Special Function Registers
– 128 bits in a subset of the internal Main RAM
– 128 bits in a subset of the Special Function Registers
Register-Indirect Addressing
– internal Main RAM (@R0, @R1, @SP [PUSH/POP])
– internal Auxiliary RAM (@R0, @R1, @DPTR)
– external Data Memory (@R0, @R1, @DPTR)
Immediate Addressing
– Program Memory (in-code 8 bit or 16 bit constant)
Base-Register-plus-Index-Register-Indirect Addressing
– Program Memory look-up table
(@DPTR+A, @PC+A)
The first three addressing modes are usable for
destination operands.
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