參數(shù)資料
型號： P8XC591
廠商： NXP Semiconductors N.V.
英文描述： HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述： 單芯片8 - CAN控制器位微控制器
文件頁數(shù)： 129/160頁
文件大?。?/td> 601K
代理商： P8XC591
2000 Jul 26
129
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
20.4
10-Bit ADC Resolution and Analog Supply
Figure 48 shows how the ADC is realized. The ADC has its
ownanalogground(AV
SS
)andapositiveanalogreference
pin (V
ref+
) connected to each end of the DAC’s
resistance-ladder. The ladder has 1023 equally spaced
taps, separated by a resistance of “R”. The first tap is
located 0.5 x R above AV
SS
, and the last tap is located
1.5 x R below V
ref+
. This gives a total ladder resistance of
1024 x R. This structure ensures that the DAC is
monotonic and results in a symmetrical quantization error
is shown in Figure 48.
For input voltages between 0 V and + 1/2 LSB, the 10-bit
result of an A/D conversion will be 00 0000 0000B =
0000H. For input voltages between (V
ref+
) - 3/2 LSB and
V
ref+
, the result of a conversion will be 11 1111 1111B =
3FFFH. AV
ref+
may be between V
DD
+0.2 V and AV
SS
-
0.2 V. AV
ref+
should be positive 0 V and AV
ref+
. If the
analog input voltage range is from 2 V to 4 V, the 10-bit
resolution can be obtained over this range if AV
ref+
= 4 V.
The result can always can always be calculated from the
following formula:
V
AV
ref+
Result = 1024
---------------
×
20.5
Power Reduction Modes
The P8xC591 has two reduced power modes of operation:
the Idle mode and the Power-down mode. These modes
are entered by setting bits in the PCON Special Function
Register. When the P8xC591 enters the Idle mode, the
following functions are disabled:
CPU
Timer T2
PWM0, PWM1
ADC
(halted)
(halted and reset)
(reset; outputs are high)
(may be enabled for operation in Idle
mode by setting bit AIDC (AUXR1.6).
In Idle mode, the following functions remain active:
Timer 0
Timer 1
Timer T3
SIO0 SIO1
External interrupts
When the P8xC591 enters the Power-down mode, the
oscillator is stopped. The Power-down mode is entered by
setting the PD bit in the PCON register. The PD bit can
only be set if the ‘WDE’ bit is 0.
Fig.51 ADC Realization.
Value 0000 0000 00
Value 1111 1111 11
is output for voltages 0 V +
1
2
LSB
is output for voltages (V
ref+
±
3
2
LSB) to V
ref+
handbook, full pagewidth
MHI053
R/2
AVref
+
R
R
R
R
R/2
AVSS
Vin
Vref
Total resistance
= 1023R
+
2
×
R/
= 1024R
COMPARATOR
DECODER
START
LSB
MSB
SUCCESSIVE
APPROXIMATION
REGISTER
SUCCESSIVE
APPROXIMATION
CONTROL LOGIC
READY
1021
1022
1023
1
0
2
3
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