參數(shù)資料
型號: P8XC591
廠商: NXP Semiconductors N.V.
英文描述: HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述: 單芯片8 - CAN控制器位微控制器
文件頁數(shù): 58/160頁
文件大小: 601K
代理商: P8XC591
2000 Jul 26
58
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
12.5.19 R
ECEIVE
B
UFFER
The global layout of the Receive Buffer is very similar to the Transmit Buffer described in the previous chapter. The
Receive Buffer is the accessible part of the RXFIFO and is located in the range between CAN Address 96 and 108. Each
message is subdivided into a Descriptor and a Data Field.
Fig.21 Example of the message storage within the RXFIFO.
Message 1 is now available in the Receive Buffer
Note that message 2 should not be read until it has been shifted to address 96 by a Release Receive
Buffer Command because this message may be in process now and due to this not fixed.
handbook, full pagewidth
MHI019
message 3
message 2
message 1
receive
buffer
window
incoming
messages
receive
FIFO
106
107
108
103
104
105
100
99
101
102
96
97
98
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