參數(shù)資料
型號(hào)： P8XC591
廠商： NXP Semiconductors N.V.
英文描述： HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述： 單芯片8 - CAN控制器位微控制器
文件頁(yè)數(shù)： 49/160頁(yè)
文件大小： 601K
代理商： P8XC591
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2000 Jul 26
49
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
12.5.17.2 Acceptance Filter Enable Register
Each defined Acceptance Filter is enabled or disabled by a certain bit located within the Acceptance Filter Enable
Register. This allows to change the Acceptance Filter Contents “on the fly” during normal operation if the corresponding
filter is disabled previously. A disabled Acceptance Filter does not allow passing of messages to the receive buffer. If all
Acceptance Filters are disabled (default after hardware reset) no messages will pass to the receive buffer at all.
Table 33
Acceptance Filter Enable Register (ACF Enable) (CAN address 30)
7
6
5
4
3
2
1
0
B4F2EN
B4F1EN
B3F2EN
B3F1EN
B2F2EN
B2F1EN
B1F2EN
B1F1EN
Table 34
Acceptance Filter Enable Register (ACF Enable)
Note, if the Single Filter Mode is selected for an Acceptance Filter Bank, this single filter is related to the corresponding
Filter 1 Enable Bit. The Filter 2 Enable Bits have no influence within Single Filter Mode.
BIT
SYMBOL
B4F2EN
NAME
VALUE
1 (enabled)
FUNCTION
ACFEN.7
Bank 4 Filter 2
Enable
Filter 2 of Bank 4 is enabled, no write access to
corresponding Mask and Code Registers is possible
0 (disabled) Filter 2 of Bank 4 is disabled, changing of corresponding
Mask and Code Registers is possible.
1 (enabled)
Filter 1 of Bank 4 is enabled, no write access to
corresponding Mask and Code Registers is possible
0 (disabled) Filter 1 of Bank 4 is disabled, changing of corresponding
Mask and Code Registers is possible.
1 (enabled)
Filter 2 of Bank 3 is enabled, no write access to
corresponding Mask and Code Registers is possible
0 (disabled) Filter 2 of Bank 3 is disabled, changing of corresponding
Mask and Code Registers is possible.
1 (enabled)
Filter 1 of Bank 3 is enabled, no write access to
corresponding Mask and Code Registers is possible
0 (disabled) Filter 1 of Bank 3 is disabled, changing of corresponding
Mask and Code Registers is possible.
1 (enabled)
Filter 2 of Bank 2 is enabled, no write access to
corresponding Mask and Code Registers is possible
0 (disabled) Filter 2 of Bank 2 is disabled, changing of corresponding
Mask and Code Registers is possible.
1 (enabled)
Filter 1 of Bank 2 is enabled, no write access to
corresponding Mask and Code Registers is possible
0 (disabled) Filter 1 of Bank 2 is disabled, changing of corresponding
Mask and Code Registers is possible.
1 (enabled)
Filter 2 of Bank 1 is enabled, no write access to
corresponding Mask and Code Registers is possible
0 (disabled) Filter 2 of Bank 1 is disabled, changing of corresponding
Mask and Code Registers is possible.
1 (enabled)
Filter 1 of Bank 1 is enabled, no write access to
corresponding Mask and Code Registers is possible
0 (disabled) Filter 1 of Bank 1 is disabled, changing of corresponding
Mask and Code Registers is possible.
ACFEN.6
B4F1EN
Bank 4 Filter 1
Enable
ACFEN.5
B3F2EN
Bank 3 Filter 2
Enable
ACFEN.4
B3F1EN
Bank 3 Filter 1
Enable
ACFEN.3
B2F2EN
Bank 2 Filter 2
Enable
ACFEN.2
B2F1EN
Bank 2 Filter 1
Enable
ACFEN.1
B1F2EN
Bank 1 Filter 2
Enable
ACFEN.0
B1F1EN
Bank 1 Filter 1
Enable
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