參數(shù)資料
型號: P8XC591
廠商: NXP Semiconductors N.V.
英文描述: HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述: 單芯片8 - CAN控制器位微控制器
文件頁數(shù): 63/160頁
文件大?。?/td> 601K
代理商: P8XC591
2000 Jul 26
63
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
14.3.4
B
AUD
R
ATE IN
M
ODE
0
The baud rate in Mode 0 is fixed to:
14.3.5
B
AUD
R
ATE IN
M
ODE
2
The baud rate in Mode 2 depends on the value of bit
SMOD1 in Special Function Register PCON. If SMOD1 =
0 (which is the value after reset), the baud rate is
1
32
of
oscillator frequency. If SMOD1 = 1, the baud rate is
1
16
of
the oscillator frequency:
2
SMOD1
14.3.6
B
AUD
R
ATE IN
M
ODE
1
AND
3
In these modes the baud rate is variable and can be
generated alternatively by a baud rate generator or by
Timer 1.
Mode 0 baud rate
oscillator frequency
-------------------------6
=
Mode 2 baud rate
-------32
oscillator frequency
×
=
14.3.7
U
SING THE
I
NTERNAL
B
AUD
R
ATE
G
ENERATOR
In Modes 1 and 3, the P8xC591 can use an internal baud
rate generator for the serial port. To enable this feature, bit
SPS (bit 7 of Special Function Register S0PSH) must be
set. Bit SMOD1 (PCON.7) controls a divide-by-2 circuit
which affect the input and output clock signal of the baud
rate generator. After reset the divide-by-2 circuit is active
and the resulting overflow output clock will be divided by 2.
The input clock of the baud rate generator is f
CLK.
The baud rate generator consists of its own free running
upward counting 12-bit timer. On overflow of this timer
(next count step after counter value FFFH) there is an
automatic 12-bit reload from the registers S0PSL and
S0PSH. The lower 8 bits of the timer are reloaded from
S0PSL, while the upper four bits are reloaded from bit 0 to
3 of register S0PSH. The baud rate timer is reloaded by
writing to S0PSH.
Fig.24 Serial Port Input Clock when using the Baud Rate Generator.
Note: The switch configuration shows the reset state.
handbook, full pagewidth
MHI025
BAUD
RATE
CLOCK
BAUD RATE
fCLK
PCON.7
(SMOD1)
0
1
÷
2
12 BIT TIMER
S0PSH
S0PSL
overflow
input
clock
.3 .2 .1 .0
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