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參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 23/160頁(yè) |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
23
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
11.3.1
P
OWER
O
FF
F
LAG
The Power Off Flag (POF) is set by on-chip circuitry when
the V
CC
level on the P8xC591 rises from 0 to 5 V. The POF
bit can be set or cleared by software allowing a user to
determine if the reset is the result of a power-on or warm
after Power-down. The V
CC
level must remain above 3 V
for the POF to remain unaffected by the V
CC
level.
11.3.2
D
ESIGN
C
ONSIDERATION
When the Idle mode is terminated by a hardware reset,
the device normally resumes program execution, from
where it left off, up to two machine cycles before the
internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access
to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when Idle is
terminated by reset, the instruction following the one
that invokes Idle should not be one that writes to a port
pin or to external memory.
11.3.3
ONCE
TM
M
ODE
The ONCE
TM
(“On-Circuit Emulation”) Mode facilities
testing and debugging of systems without the device
having to be removed from the circuit. The ONCE Mode is
invoked by:
1.
Pull ALE low while the device is in reset an PSEN is
high,
2.
Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into
a float state, and the other port pins and ALE and PSEN
are weakly pulled high. The oscillator circuit remains
active. While the device is in this mode, an emulator or test
CPU can be used to drive the circuit. Normal operation is
restored when a normal reset is applied.
11.3.4
R
EDUCED
EMI M
ODE
The ALE-Off bit, AO (AUXR.0) can be set to 0 disable the
ALE output. It will automatically become active when
required for external memory accesses and resume to the
OFF state after completing the external memory access.
11.3.5
P
OWER
C
ONTROL
R
EGISTER
(PCON)
Table 8
Power Control Register (address 87H)
Table 9
If logic 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (0XX00000).
Description of PCON bits
7
6
5
4
3
2
1
0
SMOD1
SMOD0
POF
WLE
GF1
GF0
PD
IDL
BIT
SYMBOL
DESCRIPTION
7
SMOD1
Double Baud rate
. When set to logic 1 the baud rate is doubled when the serial port
SIO0 is being used in Modes 1, 2 and 3.
Double Baud rate.
Selects SM0/FE for SCON.7 bit.
Power Off flag
.
Watchdog Load Enable
. This flag must be set by software prior to loading T3
(Watchdog Timer). It is cleared when T3 is loaded.
General purpose flag bits
.
6
5
4
SMOD0
POF
WLE
3
2
1
GF1
GF0
PD
Power-down mode select
. Setting this bit activates Power-down mode. It can only be
set if the Watchdog timer enable bit ‘WDE’ is set to logic 0.
Idle mode select
. Setting this bit activates the Idle mode.
0
IDL
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