參數(shù)資料
型號: P8XC591
廠商: NXP Semiconductors N.V.
英文描述: HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述: 單芯片8 - CAN控制器位微控制器
文件頁數(shù): 126/160頁
文件大?。?/td> 601K
代理商: P8XC591
2000 Jul 26
126
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
otherwise the bit being tested is cleared. This process is
repeated until all ten bits have been tested, at which stage
the result of the conversion is held in the successive
approximationregister.Figure 48showsaconversionflow
chart. The bit pointer identifies the bit under test. The
conversion takes four machine cycles per bit.
The end of the 10-bit conversion is flagged by control bit
ADCON.4 (ADCI). The upper 8 bits of the result are held in
Special Function Register ADCH, and the two remaining
bitsareheldinADCON.7(ADC.1)andADCON.6(ADC.0).
The user may ignore the two least significant bits in
ADCON and use the ADC as an 8-bit converter (8 upper
bits in ADCH). In any event, the total actual conversion
time is 50 machine cycles for the P8xC591. ADCI will be
set and the ADCS status flag will be reset 50 (or 24) cycles
after the command flip-flop (ADCS) is set.
ControlbitsADCON.0,ADCON.1,andADCON.2areused
to control an analog multiplexer which selects one of six
analogchannels(seeSection 20.3.1).AnADCconversion
inprogressisunaffectedbyanewsoftwareADCstart.The
result of a completed conversion remains unaffected
provided ADCI = logic 1; a new ADC conversion already in
progress is aborted when the Idle or Power-down mode is
entered. The result of a completed conversion (ADCI =
logic 1) remains unaffected when entering the Idle mode.
Fig.49 Successive Approximation ADC.
handbook, full pagewidth
MHI051
SUCCESSIVE
APPROXIMATION
REGISTER
DAC
SUCCESSIVE
APPROXIMATION
CONTROL LOGIC
START
STOP
Vin
VDAC
full scale
t/tau
VDAC
1/2
3/4
7/8
15/16
29/32
59/64
1
1
0
2
3
4
5
6
Vin
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