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| 型號： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁數(shù)： | 46/160頁 |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
46
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
12.5.16 TX E
RROR
C
OUNTER
R
EGISTER
(TXERR)
The TX Error Counter Register reflects the current value of
the Transmit Error Counter. In Operating Mode this
register appears to the CPU as a read only memory. A
writeaccesstothisregisterispossibleonlyinResetMode.
After hardware reset this register is initialised to “0”. If a
bus-off event occurs, the TX Error Counter is initialised to
127 to count the minimum protocol-defined time (128
occurrences of the Bus-Free signal). Reading the TX Error
Counter during this time gives information about the status
of the Bus-Off recovery.
If Bus Off is active, a write access to TXERR in the range
of 0 to 254 clears the Bus Off Flag and the controller will
wait for one occurrence of 11 consecutive recessive bits
(bus free) after clearing of Reset Mode.
Writing 255 to TXERR allows to initiate a CPU-driven Bus
Off event. Note, that a CPU-forced content change of the
TX Error Counter is possible only, if the Reset Mode was
entered previously. An Error or Bus Status change (Status
Register), an Error Warning or an Error Passive Interrupt
forced by the new register content will not occur, until the
Reset Mode is cancelled again. After leaving the Reset
Mode, the new TX Counter content is interpreted and the
Bus Off event is performed in the same way, as if it was
forced by a bus error event. That means, that the Reset
Mode is entered again, the TX Error Counter is initialised
to 127, the RX Counter is cleared and all concerned Status
and Interrupt Register Bits are set.
Clearing of Reset Mode now will perform the protocol
defined Bus Off recovery sequence (waiting for 128
occurrences of the Bus-Free signal).
If the Reset Mode is entered again before the end of Bus
Off recovery (TXERR > 0), Bus Off keeps active and
TXERR is frozen.
Table 30
TX Error Counter Register (TXERR) (CAN address 15)
7
6
5
4
3
2
1
0
TXERR.7
TXERR.6
TXERR.5
TXERR.4
TXERR.3
TXERR.2
TXERR.1
TXERR.0
12.5.17 A
CCEPTANCE
F
ILTER
With the help of the Acceptance Filter the CAN controller
is able to allow passing of received messages to the
RXFIFO only when the identifier bits and the Frame Type
of the received message are equal to the predefined ones
within the Acceptance Filter Registers. If at least one filter
matches, the message is copied to the receive FIFO.
The Acceptance Filter is defined by the Acceptance Code
Registers (ACRn) and the Acceptance Mask Registers
(AMRn). Within the Acceptance Code Registers the bit
patterns of messages to be received are defined. The
corresponding Acceptance Mask Registers allow defining
certain bit positions to be “don‘t care”.
The PeliCAN is designed to support four of so called
Acceptance Filter Banks. Each bank has the functionality
known from the SJA1000 with the extension, that a filter
change is possible “on the fly”. Additionally the used
Frame Format of each filter bank is programmable now.
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