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參數(shù)資料
| 型號： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁數(shù)： | 79/160頁 |
| 文件大小： | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
79
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
Fig.34 Serial Clock Synchronization.
handbook, full pagewidth
MHI035
SDA
SCL
(1)
(3)
(1)
(2)
mark
duration
space duration
(1) Another service pulls the SCL line low before the SIO “mask” duration is complete. The serial clock generator
is immediately reset and commences with the “space” duration by pulling SCL low.
(2) Another device still pulls the SCL line low after SIO1 releases SCL. The serial clock generator is forced into
the wait state until the SCL line is released.
(3) The SCL line is released, and the serial clock generator commences with the mark duration.
15.2.6
S
ERIAL
C
LOCK
G
ENERATOR
This programmable clock pulse generator provides the
SCL clock pulses when SIO1 is in the master transmitter
or master receiver mode. It is switched off when SIO1 is in
a slave mode. The programmable output clock
frequencies are: f
CLK
/120, f
CLK
/9600, and the Timer 1
overflow rate divided by eight. The output clock pulses
have a 50% duty cycle unless the clock generator is
synchronized with other SCL clock sources as described
above.
15.2.7
T
IMING AND
C
ONTROL
The timing and control logic generates the timing and
control signals for serial byte handling. This logic block
provides the shift pulses for S1DAT, enables the
comparator, generates and detects start and stop
conditions, receives and transmits acknowledge bits,
controls the master and slave modes, contains interrupt
request logic, and monitors the I
2
C bus status.
15.2.8
C
ONTROL
R
EGISTER
, S1CON
This 7-bit special function register is used by the
microcontroller to control the following SIO1 functions:
start and restart of a serial transfer, termination of a serial
transfer, bit rate, address recognition, and
acknowledgment.
15.2.9
S
TATUS
D
ECODER AND
S
TATUS
R
EGISTER
The status decoder takes all of the internal status bits and
compresses them into a 5-bit code. This code is unique for
each I
2
C bus status. The 5-bit code may be used to
generate vector addresses for fast processing of the
various service routines. Each service routine processes a
particular bus status. There are 26 possible bus states if all
four modes of SIO1 are used. The 5-bit status code is
latched into the five most significant bits of the status
register when the serial interrupt flag is set (by hardware)
and remains stable until the interrupt flag is cleared by
software. The three least significant bits of the status
register are always zero. If the status code is used as a
vector to service routines, then the routines are displaced
by eight address locations. Eight bytes of code is sufficient
for most of the service routines (see the software example
in this section).
15.2.10 T
HE
F
OUR
SIO1 S
PECIAL
F
UNCTION
R
EGISTERS
The microcontroller interfaces to SIO1 via four special
function registers. These four SFRs (S1ADR, S1DAT,
S1CON, and S1STA) are described individually in the
following sections.
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