參數(shù)資料
型號： P8XC591
廠商： NXP Semiconductors N.V.
英文描述： HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述： 單芯片8 - CAN控制器位微控制器
文件頁數(shù)： 10/160頁
文件大?。?/td> 601K
代理商： P8XC591
2000 Jul 26
10
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
P2.0/A08 to
P2.7/A15
18 to 25 24 to 31
Port 2 (P2.0 to P2.7)
: 8-bit programmable I/O port lines;
A08 to A15
: High-order address byte for external memory.
Alternate function: High-order address byte for external memory (A08-A15).
Port 2 is also used to input the upper order address during EPROM
programming and verification. A8 is on P2.0, A9 on P2.1, through A12 on
P2.4.
During reset, Port 2 will be asynchronously driven HIGH.
Port 2 has four output modes selected on a per bit basis by writing to the
P2M1 and P2M2 registers as follows:
P2M1.x
0
0
1
1
1
Open drain
Program Store Enable
output: read strobe to the external Program Memory
via Ports 0 and 2. Is activated twice each machine cycle during fetches from
external Program Memory. When executing out of external Program Memory
two activations of PSEN are skipped during each access to external Data
Memory. PSEN is not activated (remains HIGH) during no fetches from
external Program Memory. PSEN can sink/source 8 LSTTL inputs. It can
drive CMOS inputs without external pull-ups.
Address Latch Enable
output. Latches the low byte of the address during
access of external memory in normal operation. It is activated every six
oscillator periods except during an external Data Memory access. ALE can
sink/source 8 LSTTL inputs. It can drive CMOS inputs without an external
pull-up. To prohibit the toggling of ALE pin (RFI noise reduction) the bit A0
(SFR: AUXR.0) must be set by software; see Table 4.
PROG
: the programming pulse input; alternative function for the P87C591.
External Access
input. If, during reset, EA is held at a TTL level HIGH the
CPU executes out of the internal Program Memory. If, during reset, EA is held
at a TTL level LOW the CPU executes out of external Program Memory via
Port 0 and Port 2. EA is not allowed to float. EA is latched during reset and
don’t care after reset.
V
PP
: the programming supply voltage; alternative function for the P87C591.
Port 0
: 8-bit open-drain bidirectional I/O port.
During reset, Port 0 is HIGH-Impedance (Tri-State).
P2M2.x
0
1
0
Mode Description
Pseudo-bidirectional (standard c51 configuration default)
Push-Pull
High impedance
PSEN
26
32
ALE/PROG
27
33
EA/V
PP
29
35
P0.0/AD0 to
P0.7/AD7
30 to 37 36 to 43
AD7 to AD0
: Multiplexed Low-order address and Data bus for external
memory. During these accesses internal pull-ups are activated. Port 0 can
sink/source up to 8 LSTTL inputs.
Analog to Digital Conversion Reference Resistor:
High-end.
Analog ground.
AV
ref+
AV
SS
38
39
44
1
SYMBOL
PIN
DESCRIPTION
QFP44
PLCC44
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