參數(shù)資料
型號: P8XC591
廠商: NXP Semiconductors N.V.
英文描述: HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述: 單芯片8 - CAN控制器位微控制器
文件頁數(shù): 146/160頁
文件大?。?/td> 601K
代理商: P8XC591
2000 Jul 26
146
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
25 AC CHARACTERISTICS
V
DD
= 5 V
±
5%; V
SS
= 0 V; T
amb
=
40
°
C to +85
°
C; C
L
= 100 pF for Port 0, ALE and PSEN; C
L
= 80 pF for all other
outputs unless otherwise specified.
SYMBOL
PARAMETER
12 MHz CLOCK
VARIABLE CLOCK
UNIT
MIN.
MAX.
MIN.
MAX.
External Program Memory;
see Fig.55
1/f
CLK
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
External Data Memory;
see Fig.56
and
Fig.57
System clock frequency; see Note 1
ALE pulse width
address valid to ALE LOW
address hold after ALE LOW
ALE LOW to valid instruction in
ALE LOW to PSEN LOW
PSEN pulse width
PSEN LOW to valid instruction in
input instruction hold after PSEN
input instruction float after PSEN
address to valid instruction in
PSEN LOW to address float
3.5
12
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
58
17
17
17
80
0
t
CLK
25
0.5 t
CLK
25
0.5 t
CLK
25
0.5 t
CLK
25
1.5 t
CLK
45
0
102
65
17
128
10
2 t
CLK
65
1.5 t
CLK
60
0.5 t
CLK
25
2.5 t
CLK
80
10
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
WHQX
t
QVWH
t
RLAZ
t
WHLH
External Clock;
see Fig.58
RD pulse width
WR pulse width
RD LOW to valid data in
data hold after RD
data float after RD
ALE LOW to valid data in
address to valid data in
ALE LOW to RD or WR LOW
address valid to RD or WR LOW
data valid to WR transition
data hold after WR
data valid time WR HIGH
RD LOW to address float
RD or WR HIGH to ALE HIGH
150
150
0
75
92
12
6
162
17
3 t
CLK
100
3 t
CLK
100
0
1.5 t
CLK
50
2 t
CLK
75
0.5 t
CLK
30
0.5 t
CLK
25
3.5 t
CLK
130
0.5 t
CLK
25
ns
ns
ns
ns
ns
ns
118
63
183
210
175
0
67
2.5 t
CLK
90
t
CLK
20
4 t
CLK
150
4.5 t
CLK
165 ns
1.5 t
CLK
+ 50
0
0.5 t
CLK
+ 25
ns
ns
ns
ns
ns
ns
ns
t
CHCX
t
CLCX
t
CLCH
t
CHCL
high time
low time
rise time
fall time
37.5
37.5
45.8
45.8
20
20
t
CLK
×
0.45
t
CLK
×
0.45
t
CLK
×
0.55
t
CLK
×
0.55
20
20
ns
ns
ns
ns
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