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參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 60/160頁(yè) |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
60
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
13 SERIAL I/O
The P8xC591 is equipped with three independent serial
ports: CAN, SIO0 and SIO1. SIO0 is a Standard Serial
Interface UART with enhanced functionality. In following
there will be one Section describing the Standard UART
functionality and an extra Section for Enhanced UART.
SIO1 accommodates the I
2
C bus.
14 SIO0 STANDARD SERIAL INTERFACE UART
The serial port is full duplex, meaning it can transmit and
receive simultaneously. It is also receive-buffered,
meaning it can commence reception of a second byte
before a previously received byte has been read from the
register. (However, if the first byte still hasn’t been read by
the time reception of the second byte is complete, one of
the bytes will be lost.) The serial port receive and transmit
registers are both accessed at Special Function Register
transmit registers are both accessed at Special Function
Register S0BUF. Writing to S0BUF loads the transmit
register, and reading S0BUF accesses a physically
separate receive register.
The serial port can operate in 4 modes (one synchronous
mode, three asynchronous modes). The baud rate clock
for the serial port is derived from the oscillator frequency
(mode 0, 2) or generated either by timer 1 or by dedicated
baud rate generator (mode 1, 3).
Mode 0 Shift Register (Synchronous) Mode:
Serial data enters and exits through RxD. TxD
outputs the shift clock. 8 bits are transmitted/
received (LSB first). The baud rate is fixed
1
6
the
oscillator frequency.
Mode 1 8-bit UART, Variable Baud Rate:
10 bits are transmitted (through TxD) or received
(through RxD): a start bit (0), 8 data bits (LSB
first), and a stop bit (1). On receive, the stop bit
goes into RB8 in Special Function Register
SCON. The baud rate is variable.
Mode 2 9-bit UART, Fixed Baud Rate:
11 bits are transmitted (through TxD) or received
(through RxD): start bit (0), 8 data bits (LSB first),
a programmable 9
th
data bit, and a stop bit (1).
On Transmit, the 9
th
data bit (TB8 in SCON) can
be assigned the value of 0 or 1. Or, for example,
the parity bit (P, in the PSW) could be moved into
TB8. On receive, the 9
th
data bit goes into RB8 in
Special Function Register SCON, while the stop
bit ignored. The baud rate is programmable to
either
1
16
or
1
32
the oscillator frequency.
Mode 3 9-bit UART, Variable Baud Rate:
11 bits are transmitted (through TxD) or received
(through RxD): start bit (0), 8 data bits (LSB first),
a programmable 9
th
data bit, and a stop bit (1). In
fact,Mode3isthesameasMode2inallrespects
except baud rate. The baud rate in Mode 3 is
variable.
In all four modes, transmission is initiated by any
instruction that uses S0BUF as a destination register.
Reception is initiated in Mode 0 by the condition RI = 0 and
REN = 1. Reception is initiated in the other modes by the
incoming start bit if REN = 1.
14.1
Multiprocessor Communications
Modes 2 and 3 have a special provision for multiprocessor
communications. In these modes, 9 data bits are received.
The 9
th
one goes into RB8. Then comes a stop bit. The
port can be programmed such that when the stop bit is
received, the serial port interrupt will be activated only if
RB8 = 1. This feature is enabled by setting bit SM2 in
SCON. A way to use this feature in multiprocessor
systems is as follows:
When the master processor wants to transmit a block of
data to one of several slaves, it first send out an address
byte which indentifies the target slave. An address byte
differs from a data byte in that the 9
th
bit is 1 in an address
byte and 0 in a data byte. With SM2 = 1, no slave will be
interrupted by a data byte. An address byte, however, will
interrupt all slaves, so that each slave can examine the
received byte and see if it is being addressed. The
addressed slave will clear its SM2 bit and prepare to
receive the data bytes that will be coming. The slaves that
weren’t being addressed leave their SM2s set and go on
about their business, ignoring the coming data bytes.
SM2 has no effect in Mode 0, and in Mode 1 can be used
to check the validity of the stop bit. In a Mode 1 reception,
if SM2 = 1, the receive interrupt will not be activated unless
a valid stop bit is received.
14.2
Serial Port Control Register
The serial port control and status register is the Special
Function Register SCON, shown in Table 38, 40 and 41.
This register contains not only the mode selection bits, but
also the 9
th
data bit for transmit and receive (TB8 and
RB8), and the serial port interrupt bits (TI and RI).
S0BUF is the receive and transmit buffer of serial
interface. Writing to S0BUF loads the transmit register and
initiates transmission. Reading out S0BUF accesses a
physically separate receive register.
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