參數(shù)資料
型號： P8XC591
廠商： NXP Semiconductors N.V.
英文描述： HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述： 單芯片8 - CAN控制器位微控制器
文件頁數(shù)： 22/160頁
文件大?。?/td> 601K
代理商： P8XC591
2000 Jul 26
22
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
11 LOW POWER MODES
11.1
Stop Clock Mode
The static design enables the clock speed to be reduced
down to 0 MHz (stopped). When the oscillator is stopped,
the RAM and Special Function Registers retain their
values. This mode allows step-by-step utilization and
permits reduced system power consumption by lowering
the clock frequency down to any value. For lowest power
consumption the Power-down mode is suggested.
11.2
Idle Mode
In the Idle mode (see Table 7), the CPU puts itself to sleep
while all of the on-chip peripherals stay active. The
instruction to invoke the idle mode is the last instruction
executed in the normal operating mode before the Idle
mode is activated. The CPU contents, the on-chip RAM,
andallofthespecialfunctionregistersremainintactduring
this mode. The Idle mode can be terminated either by any
enabled interrupt (at which time the process is picked up
at the interrupt service routine and continued), or by a
hardware reset which starts the processor in the same
manner as a Power-on reset.
11.3
Power-down Mode
To save even more power, a Power-down mode (see
Table 7) can be invoked by software. In this mode, the
oscillatorisstoppedandtheinstructionthatinvokedPower
Down is the last instruction executed. The on-chip RAM
and Special Function Registers retain their values down to
2.0 V and care must be taken to return V
CC
to the minimum
specifiedoperatingvoltagesbeforethePower-downMode
is terminated.
A hardware reset or external interrupt can be used to exit
from Power-down. The Wake-up from Power-down bit,
WUPD (AUXR1.3) must be set in order for an interrupt to
cause a Wake-up from Power-down. Reset redefines all
the SFRs but does not change the on-chip RAM. A
Wake-up allows both the SFRs and the on-chip RAM to
retain their values.
To properly terminate Power-down the reset or external
interrupt should not be executed before V
CC
is restored to
its normal operating level and must be held active long
enough for the oscillator to restart and stabilize (normally
less than 10 ms).
Table 7
Status of external pins during Idle and Power-down modes
With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts
the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be
executed after RETI will be the one following the instruction that put the device into Power-down.
MODE
MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
PWM0/
PWM1
Idle
internal
external
internal
external
1
1
0
0
1
1
0
0
port data
float
port data
float
port data
port data
port data
port data
port data
address
port data
port data
port data
port data
port data
port data
high
high
high
high
Power-down
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