參數(shù)資料
型號(hào): P8XC591
廠商: NXP Semiconductors N.V.
英文描述: HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述: 單芯片8 - CAN控制器位微控制器
文件頁數(shù): 115/160頁
文件大?。?/td> 601K
代理商: P8XC591
2000 Jul 26
115
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
16.1.2
T
IMER
T2 E
XTENSION
When a 6 MHz oscillator is used, a 16-bit overflow on
Timer T2 occurs every 65.5, 131, 262, or 524 ms,
depending on the prescaler division ratio; i.e., the
maximum cycle time is approximately 0.5 seconds. In
applications where cycle times are greater than 0.5
seconds, it is necessary to extend Timer T2. This is
achieved by selecting f
CLK
/6 as the clock source (set
T2MS0, reset T2MS1), setting the prescaler division ration
to
1
8
(set T2P0, set T2P1), disabling the byte overflow
interrupt (reset T2lS0) and enabling the 16-bit overflow
interrupt (set T2lS1). The following software routine is
written for a three-byte extension which gives a maximum
cycle time of approximately 2400 hours.
OVINT:
PUSH ACO
PUSH PSW
INC TlMEX1 ; increment first byte (low order) of
extended timer
MOV A,TlMEX1
JNZ INTEX
; jump to INTEX if; there is no
overflow
INC TlMEX2 ; increment second byte
MOV A,TlMEX2
JNZ INTEX
; jump to INTEX if there is no
overflow
INC TlMEX3 ; increment third byte (high order)
; save accumulator
; save status
INTEX:
CLR T2OV
POP PSW
POP ACC
RETI
; reset interrupt flag
; restore status
; restore accumulator
; return from interrupt
16.1.3
T
IMER
T2, C
APTURE AND
C
OMPARE
L
OGIC
Timer T2 is connected to four 16-bit capture registers and
three 16-bit compare registers. A capture register may be
used to capture the contents of Timer T2 when a transition
occurs on its corresponding input pin. A compare register
may be used to set or reset port 3 output pins at certain
pre-programmable time intervals. The combination of
Timer T2 and the capture and compare logic is very
powerful in applications involving rotating machinery,
automotive injection systems, etc. Timer T2 and the
capture and compare logic are shown in Figure 45.
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