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參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 81/160頁(yè) |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
81
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
15.2.12 T
HE
C
ONTROL
R
EGISTER
, S1CON
The CPU can read from and write to this 8-bit, directly addressable SFR. Two bits are affected by the SIO1 hardware:
the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when a STOP condition is present on the
I
2
C bus. The STO bit is also cleared when ENS1 = 0.
Table 55
Address Register S1CON (address D8H)
Table 56
Description of S1CON (D8H) bits
7
6
5
4
3
2
1
0
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
BIT
SYMBOL
DESCRIPTION
7
6
5
CR2
ENS1
STA
Clock rate bit 2, see Table 57.
Enable serial I/O
. ENS1 = 0: I
2
C I/O disabled and reset. ENS1 = 1: serial I/O enabled.
START flag.
When this bit is set in slave mode, the hardware checks the I
2
C-bus and generates
a START condition if the bus is free or after the bus becomes free. If the device operates in
master mode it will generate a repeated START condition.
STOP flag
. If this bit is set in a master mode a STOP condition is generated. A STOP condition
detected on the I
2
C-bus clears this bit. This bit may also be set in slave mode in order to recover
from an error condition. In this case no STOP condition is generated to the I
2
C-bus, but the
hardware releases the SDA and SCL lines and switches to the not selected receiver mode. The
STOP flag is cleared by the hardware.
Serial Interrupt flag.
This flag is set and an interrupt request is generated, after any of the
following events occur:
A START condition is generated in master mode.
The own slave address has been received during AA = 1.
The general call address has been received while S1ADR.0 and AA = 1.
A data byte has been received or transmitted in master mode (even if arbitration is lost).
A data byte has been received or transmitted as selected slave.
A STOP or START condition is received as selected slave receiver or transmitter.
While the SI flag is set, SCL remains LOW and the serial transfer is suspended. SI must be reset
by software.
Assert Acknowledge flag.
When this bit is set, an acknowledge is returned after any one of the
following conditions:
Own slave address is received.
General call address is received (S1ADR.0 = 1).
A data byte is received, while the device is programmed to be a master receiver.
A data byte is received. while the device is a selected slave receiver.
When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when
the own address or general call address is received.
Clock rate bits 1 and 0; see Table 57.
4
STO
3
SI
2
AA
1
0
CR1
CR0
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