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參數(shù)資料
| 型號： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁數(shù)： | 122/160頁 |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
122
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
18 PULSE WIDTH MODULATED OUTPUTS
TheP8xC591containstwoPulseWidthModulated(PWM)
output channels (see Fig.47). These channels generate
pulses of programmable length and interval. The repetition
frequency is defined by an 8-bit prescaler PWMP, which
supplies the clock for the counter. The prescaler and
counter are common to both PWM channels. The 8-bit
counter counts modulo 255, i.e., from 0 to 254 inclusive.
The value of the 8-bit counter is compared to the contents
of two registers: PWM0 and PWM1.
Provided the contents of either of these registers is greater
than the counter value, the corresponding PWM0 or
PWM1 output is set LOW. If the contents of these registers
are equal to, or less than the counter value, the output will
be HIGH. The pulse-width-ratio is therefore defined by the
contents of the registers PWM0 and PWM1. The
pulse-width-ratio is in the range of
0
255
to
255
255
and may
be programmed in increments of
1
255
.
Buffered PWM outputs may be used to drive DC motors.
The rotation speed of the motor would be proportional to
the contents of PWMn. The PWM outputs may also be
configured as a dual DAC.
In this application, the PWM outputs must be integrated
using conventional operational amplifier circuitry. If the
resulting output voltages have to be accurate, external
buffers with their own analog supply should be used to
buffer the PWM outputs before they are integrated.
The repetition frequency f
PWM
, at the PWMn outputs is
given by:
This gives a repetition frequency range of 184 Hz to
47 kHz (at f
CLK
= 12 MHz). By loading the PWM registers
with either 00H or FFH, the PWM channels will output a
constant HIGH or LOW level, respectively. Since the 8-bit
counter counts modulo 255, it can never actually reach the
value of the PWM registers when they are loaded with
FFH.
Whenacompareregister(PWM0 or PWM1)isloadedwith
a new value, the associated output is updated
immediately. It does not have to wait until the end of the
current counter period. Both PWMn output pins are driven
by push-pull drivers. These pins are not used for any other
purpose.
f
PWM
f
+
PWMP
1
(
)
255
×
---------------------------------------------------
=
Fig.47 Functional diagram of Pulse Width Modulated outputs.
handbook, full pagewidth
MHI048
fCLK
PWMP
PWM1
PRESCALER
8-BIT COUNTER
PWM0
I
8-BIT COMPARATOR
8-BIT COMPARATOR
OUTPUT
BUFFER
PWM1
OUTPUT
BUFFER
PWM0
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