參數(shù)資料
型號(hào)： P8XC591
廠商： NXP Semiconductors N.V.
英文描述： HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述： 單芯片8 - CAN控制器位微控制器
文件頁數(shù)： 41/160頁
文件大?。?/td> 601K
代理商： P8XC591
2000 Jul 26
41
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
12.5.9
B
US
T
IMING
R
EGISTER
1 (BTR1)
The contentsof Bus TimingRegister 1 definesthe length of thebitperiod, the locationof the sample point andthe number
of samples to be taken at each bit time. This register can be accessed (read/write) if the Reset Mode is active. In
Operating Mode, this register is read only.
Table 20
Bus Timing Register 1 (BTR1) (CAN address 7)
12.5.9.1
Sampling (SAM)
Table 21
Sampling (SAM)
12.5.9.2
Time Segment 1 (TSEG1) and Time Segment 2 (TSEG2)
TSEG1 and TSEG2 determine the number of clock cycles per bit period and the location of the sample point:
7
6
5
4
3
2
1
0
SAM
TSEG2.2
TSEG2.1
TSEG2.0
TSEG1.3
TSEG1.2
TSEG1.1
TSEG1.0.
BIT
VALUE
FUNCTION
SAM
1 (triple)
The bus is sampled three times
-> recommended for low/medium speed buses (class A and B) where filtering
spikes on the bus-line is beneficial
The bus is sampled once
-> recommended for high speed buses (SAE class C)
0 (once)
tSYNCSEG
1
tscl
×
=
tTSEG1
tscl
8
TSEG1.3
×
4
TSEG1.2
2
TSEG1.1
TSEG1.0
1
+
+
×
+
×
+
(
)
×
=
tTSEG2
tscl
4
TSEG2.2
2
TSEG2.1
TSEG2.0
1
+
+
×
+
×
(
)
×
=
handbook, full pagewidth
μ
C:
MHI011
tscl
tSYNCSEG
sync.
seg.
CAN:
sync.
seg.
tTSEG1
nominal bit time
tTSEG2
TSEG1
e.g.
BRP = 000010b
TSEG1 = 0101b
TSEG2 = 010b
TSEG2
TSEG1
sample point(s)
tCLK
baud rate prescaler
Fig.12 General structure of a bit period.
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