參數(shù)資料
型號: IBM21P100BGB
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA304
封裝: 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304
文件頁數(shù): 98/140頁
文件大?。?/td> 2032K
代理商: IBM21P100BGB
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
Configuration Registers
Page 52 of 131
ppb11_pcix_regs.fm.03
July 9, 2001
5.2.4.27 Capabilities Pointer Register
The Capabilities Pointer register specifies a pointer to a capabilities list item in configuration space.
5.2.4.28 Reserved Registers
These registers are reserved and return zeros when read.
5.2.4.29 Interrupt Line Register
The Interrupt Line register is a read/write register that is used to communicate interrupt line routing informa-
tion between initialization code and the device driver. If a bridge does not implement an interrupt signal pin,
then POST code must write x‘FF’ to this register.
Address Offset
x‘34’
Access
Read only
Reset Value
x‘80’
Capabilities Pointer
76
54
321
0
Bit(s)
Access
Field Name and Description
7:0
RO
Capabilities Pointer
Read-only pointer to a capabilities list in configuration space.
Address Offset
x‘35’
Width
24 bits
Access
Read only
Reset Value
x‘000000’
Address Offset
x‘3C’
Access
Read/Write
Reset Value
x‘XX’
Interrupt Line
76
54
321
0
Bit(s)
Access
Field Name and Description
7:0
RW
Interrupt Line
POST code must initialize this register to x‘FF’.
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