
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
Configuration Registers
Page 68 of 131
ppb11_pcix_regs.fm.03
July 9, 2001
5.2.5.10 Discard Timer Control Register
The Discard Timer Control register controls the duration and enabling of the discard timers.
There is a unique Discard Timer for every delayed transaction enqueued in the bridge. A Discard Timer
begins counting at the receipt of a delayed transaction in conventional PCI mode. The timer is reset each time
the initiating bus master retries the transaction. The timer is stopped and reset when the transaction is
completed. If a Discard Timer expires, the associated transaction is discarded (data buffers and control
resources are freed) and the appropriate status bit is set in the Retry and Timer Status register.
Address Offset
x‘68’
Access
Read/Write
Reset Value
x‘00’
Reserved
Primar
y
D
is
card
T
im
e
r
S
hort
D
urat
ion
Seconda
ry
Di
s
c
ard
T
im
er
Short
D
urat
ion
P
rimar
y
D
is
c
a
rd
Ti
m
e
r
Dis
able
Seconda
ry
Di
s
c
ard
T
im
er
Disable
7654321
0
Bit(s)
Access
Field Name and Description
7:4
RO
Reserved
3RW
Primary Discard Timer Short Duration
Controls the number of PCI clocks that the primary discard timer allows before it expires.
0
Use bit 8 of the Bridge Control register to indicate how many PCI clocks should be allowed before the
primary discard timer expires.
1
Use 26 PCI clocks for the value of the primary discard timer.
2RW
Secondary Discard Timer Short Duration
Controls the number of PCI clocks that the secondary discard timer allows before it expires.
0
Use bit 9 of the Bridge Control register to indicate how many PCI clocks should be allowed before the
secondary discard timer expires.
1
Use 26 PCI clocks for the value of the secondary discard timer.
1RW
Primary Discard Timer Disable
Controls the disabling of the primary discard timer in conjunction with bit 11 of the Bridge Control register.
0
Enable the primary discard timer
1
Disable primary discard timer
0RW
Secondary Discard Timer Disable
Controls the disabling of the secondary discard timer in conjunction with bit 11 of the Bridge Control register.
0
Enable the secondary discard timer
1
Disable secondary discard timer